Dennis/srdl2sv
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Dennis 27c4e9de3c
Add proper logging mechanism to application 
This mechanism has custom coloring, support to dump in file and
on the commandline and support to turn either or both off. cli/cli.py
provies a function that can be called in each module to instantiate
a logger for that module.
2021-05-10 00:59:52 +02:00
srdl2sv
Add proper logging mechanism to application
2021-05-10 00:59:52 +02:00
.gitignore
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
LIMITATIONS.md
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
Description
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asicfpgahardware-description-languagehdlrdlregister-description-languageregisterssystemrdlsystemrdl-compilersystemverilogverilog
713 KiB
Languages
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%