Dennis/srdl2sv
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Dennis 59b91536ed Propgate logger through components and let top-level write SV 
Previously, the SystemVerilog was simply written to the shell. This
started to become too long to be readable. Now, the application dumps
everything to the output directory that is defined on the command line
(or the default).

Temporary workaround: the AddrMap component's RTL is completely
overwritten by the Register's RTL. This is temporary until the AddrMap
also uses a YAML file.
2021-05-11 00:28:52 +02:00
srdl2sv
Propgate logger through components and let top-level write SV
2021-05-11 00:28:52 +02:00
.gitignore
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
LIMITATIONS.md
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
Description
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asicfpgahardware-description-languagehdlrdlregister-description-languageregisterssystemrdlsystemrdl-compilersystemverilogverilog
713 KiB
Languages
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%