mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2025-04-19 13:02:57 +00:00
570 lines
22 KiB
Python
570 lines
22 KiB
Python
import importlib.resources as pkg_resources
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import math
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import sys
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import yaml
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import itertools
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from systemrdl import node
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# Local modules
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from components.component import Component
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from components.field import Field
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from . import templates
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class Register(Component):
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# Save YAML template as class variable
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templ_dict = yaml.load(
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pkg_resources.read_text(templates, 'register.yaml'),
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Loader=yaml.FullLoader)
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def __init__(
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self,
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obj: node.RegNode,
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parents_dimensions: list,
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parents_stride: list,
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config: dict,
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glbl_settings: dict):
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super().__init__(obj, config)
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# Save and/or process important variables
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self.__process_variables(obj, parents_dimensions, parents_stride, glbl_settings)
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self.config['external'] = obj.external
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# Create RTL for fields of initial, non-alias register
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for field in obj.fields():
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# Use range to save field in an array. Reason is, names are allowed to
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# change when using an alias
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field_range = ':'.join(map(str, [field.msb, field.lsb]))
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self.children[field_range] = Field(field,
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self.total_array_dimensions,
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self.config,
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glbl_settings)
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# Get properties from field that apply to whole register
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for key in self.properties:
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self.properties[key] |= self.children[field_range].properties[key]
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# Perform sanity check
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self.children[field_range].sanity_checks()
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def create_rtl(self):
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# Create RTL of children
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if self.config['external']:
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[x.create_external_rtl() for x in self.children.values()]
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else:
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[x.create_internal_rtl() for x in self.children.values()]
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# Create generate block for register and add comment
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if self.dimensions and not self.generate_active:
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self.rtl_header.append("generate")
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# Add N layers of for-loop starts
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for i in range(self.dimensions):
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self.rtl_header.append(
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Register.templ_dict['generate_for_start'].format(
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iterator = ''.join(['gv_', chr(97+i+self.parents_depths)]),
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limit = self.array_dimensions[i]))
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# Add decoders for all registers & aliases
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self.__add_address_decoder()
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# Fields will be added by get_rtl()
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# Add interrupt logic
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self.__add_interrupts()
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# Add assignment of read-wires
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self.__add_sw_mux_assignments()
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# Add N layers of for-loop end
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for i in range(self.dimensions-1, -1, -1):
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self.rtl_footer.append(
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Register.templ_dict['generate_for_end'].format(
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dimension = ''.join(['gv_', chr(97+i)])))
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if self.dimensions and not self.generate_active:
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self.rtl_footer.append("\nendgenerate\n")
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# Add wire instantiation
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if not self.generate_active:
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# We can/should only do this if there is no encapsulating
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# regfile which create a generate
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self.__add_signal_instantiations()
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# Create comment and provide user information about register he/she is looking at
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self.rtl_header = [
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Register.templ_dict['reg_comment'].format(
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name = self.obj.inst_name,
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dimensions = self.dimensions,
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depth = self.depth),
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*self.rtl_header
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]
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def __add_interrupts(self):
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# Semantics on the intr and halt property:
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# a) The intr and halt register properties are outputs; they should only
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# occur on the right-hand side of an assignment in SystemRDL.
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# b) The intr property shall always be present on a intr register even if
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# no mask or enables are specified.
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# c) The halt property shall only be present if haltmask or haltenable is
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# specified on at least one field in the register.
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if self.properties['intr']:
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self.rtl_footer.append(Register.templ_dict['interrupt_comment']['rtl'])
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self.rtl_footer.append(
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self.process_yaml(
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Register.templ_dict['interrupt_intr'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'list': ') || |('.join([
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x.itr_masked for x in self.children.values() if x.itr_masked])
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}
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)
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)
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if self.properties['halt']:
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self.rtl_footer.append(
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self.process_yaml(
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Register.templ_dict['interrupt_halt'],
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{'path': self.path_underscored,
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'genvars': self.genvars_str,
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'list': ') || |('.join([
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x.itr_haltmasked for x in self.children.values() if x.itr_haltmasked])
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}
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)
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)
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def __add_sw_mux_assignments(self):
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accesswidth = self.obj.get_property('accesswidth') - 1
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self.rtl_footer.append("")
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for na_map in self.name_addr_mappings:
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current_bit = 0
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# Start tracking errors
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# Handle fields
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list_of_fields = []
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bytes_read = set()
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bytes_written = set()
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for field in self.children.values():
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if na_map[0] in field.readable_by:
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empty_bits = field.lsb - current_bit
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current_bit = field.msb + 1
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if empty_bits > 0:
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list_of_fields.append(
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f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
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list_of_fields.append("{}_q{}".format(field.path_underscored, self.genvars_str))
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# Add to appropriate bytes
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[bytes_read.add(x) for x in range(field.lsbyte, field.msbyte+1)]
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if na_map[0] in field.writable_by:
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# Add to appropriate bytes
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[bytes_written.add(x) for x in range(field.lsbyte, field.msbyte+1)]
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empty_bits = accesswidth - current_bit + 1
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no_reads = not list_of_fields
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if empty_bits > 0:
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list_of_fields.append(
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f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
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# Create list of mux-inputs to later be picked up by carrying addrmap
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self.sw_mux_assignment_var_name.append(
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(
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self.process_yaml(
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Register.templ_dict['sw_data_assignment_var_name'],
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{'path': na_map[0],
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'accesswidth': accesswidth}
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),
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self.process_yaml(
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Register.templ_dict['sw_rdy_assignment_var_name'],
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{'path': na_map[0]}
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),
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self.process_yaml(
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Register.templ_dict['sw_err_assignment_var_name'],
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{'path': na_map[0]}
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),
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na_map[1], # Start addr
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)
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)
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# Return an error if *no* read or *no* write can be succesful.
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# If some bits cannot be read/write but others are succesful, don't return
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# an error.
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#
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# Furthermore, consider an error indication that is set for external registers
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bytes_read_format = ["b2r.byte_en[{}]".format(x) for x in list(map(str, bytes_read))]
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bytes_written_format = ["b2r.byte_en[{}]".format(x) for x in list(map(str, bytes_written))]
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sw_err_condition_vec = []
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sw_err_condition_vec.append(self.process_yaml(
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Register.templ_dict['sw_err_condition'],
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{'rd_byte_list_ored':
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' || '.join(bytes_read_format) if bytes_read else "1'b0",
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'wr_byte_list_ored':
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' || '.join(bytes_written_format) if bytes_written else "1'b0"}
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)
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)
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if self.config['external']:
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if bytes_read:
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for field in self.children.values():
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sw_err_condition_vec.append(self.process_yaml(
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Register.templ_dict['external_err_condition'],
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{'path': '__'.join([na_map[0], field.name]),
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'genvars': self.genvars_str,
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'rd_or_wr': 'r'}
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)
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)
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if bytes_written:
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for field in self.children.values():
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sw_err_condition_vec.append(self.process_yaml(
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Register.templ_dict['external_err_condition'],
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{'path': '__'.join([na_map[0], field.name]),
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'genvars': self.genvars_str,
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'rd_or_wr': 'w'}
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)
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)
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sw_err_condition = ' || '.join(sw_err_condition_vec)
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# If registers are implemented in RTL, they will be ready immediately. However,
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# if they are defined as 'external', there might be some delay
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if self.config['external']:
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if bytes_read:
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sw_rdy_condition_vec = ['(']
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for field in self.children.values():
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sw_rdy_condition_vec.append(self.process_yaml(
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Register.templ_dict['external_rdy_condition'],
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{'path': '__'.join([na_map[0], field.name]),
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'genvars': self.genvars_str,
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'rd_or_wr': 'r'}
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)
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)
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sw_rdy_condition_vec.append(' && ')
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sw_rdy_condition_vec.pop()
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sw_rdy_condition_vec.append(' && b2r.r_vld)')
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if bytes_read and bytes_written:
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sw_rdy_condition_vec.append(' || ')
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if bytes_written:
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sw_rdy_condition_vec.append('(')
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for field in self.children.values():
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sw_rdy_condition_vec.append(self.process_yaml(
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Register.templ_dict['external_rdy_condition'],
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{'path': '__'.join([na_map[0], field.name]),
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'genvars': self.genvars_str,
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'rd_or_wr': 'w'}
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)
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)
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sw_rdy_condition_vec.append(' && ')
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sw_rdy_condition_vec.pop()
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sw_rdy_condition_vec.append(' && b2r.w_vld)')
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sw_rdy_condition = ''.join(sw_rdy_condition_vec)
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else:
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sw_rdy_condition = "1'b1"
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# Assign all values
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self.rtl_footer.append(
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self.process_yaml(
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Register.templ_dict['sw_data_assignment'],
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{'sw_data_assignment_var_name': self.sw_mux_assignment_var_name[-1][0],
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'sw_rdy_assignment_var_name': self.sw_mux_assignment_var_name[-1][1],
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'sw_err_assignment_var_name': self.sw_mux_assignment_var_name[-1][2],
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'genvars': self.genvars_str if not no_reads else '',
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'rdy_condition': sw_rdy_condition,
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'err_condition': sw_err_condition,
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'list_of_fields': ', '.join(reversed(list_of_fields))}
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)
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)
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def create_mux_string(self):
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for mux_tuple in self.sw_mux_assignment_var_name:
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# Loop through lowest dimension and add stride of higher
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# dimension once everything is processed
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if self.total_array_dimensions:
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vec = [0]*len(self.total_array_dimensions)
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for i in self.eval_genvars(vec, 0, self.total_array_dimensions):
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yield (mux_tuple, i)
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else:
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yield(mux_tuple, (0, ''))
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def eval_genvars(self, vec, depth, dimensions):
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for i in range(dimensions[depth]):
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vec[depth] = i
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if depth == len(dimensions) - 1:
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yield (
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eval(self.genvars_sum_str_vectorized),
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'[{}]'.format(']['.join(map(str, vec)))
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)
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else:
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yield from self.eval_genvars(vec, depth+1, dimensions)
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vec[depth] = 0
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def __add_address_decoder(self):
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# Assign variables from bus
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self.obj.current_idx = [0]
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if self.total_dimensions:
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access_wire_assign_field = 'access_wire_assign_multi_dim'
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else:
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access_wire_assign_field = 'access_wire_assign_1_dim'
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for i, x in enumerate(self.name_addr_mappings):
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self.rtl_header.append(
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self.process_yaml(
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Register.templ_dict['access_wire_comment'],
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{'path': x[0],
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'alias': '(alias)' if i > 0 else '',
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}
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)
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)
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self.rtl_header.append(
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self.process_yaml(
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Register.templ_dict[access_wire_assign_field],
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{'path': x[0],
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'addr': x[1],
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'genvars': self.genvars_str,
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'genvars_sum': self.genvars_sum_str,
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'depth': self.depth,
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}
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)
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)
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# A wire that indicates a read is required
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if self.properties['sw_rd_wire']:
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# Check if a read is actually possible. Otherwise provide a wire
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# that is tied to 1'b0
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if self.properties['sw_rd']:
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self.rtl_header.append(
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self.process_yaml(
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Register.templ_dict['read_wire_assign'],
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{'path': x[0],
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'addr': x[1],
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'genvars': self.genvars_str,
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'genvars_sum': self.genvars_sum_str,
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'depth': self.depth,
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}
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)
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)
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else:
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self.rtl_header.append(
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self.process_yaml(
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Register.templ_dict['read_wire_assign_0'],
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{'path': x[0],
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'genvars': self.genvars_str,
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}
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)
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)
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# A wire that indicates a write is required
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if self.properties['sw_wr_wire']:
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# Check if a write is actually possible. Otherwise provide a wire
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# that is tied to 1'b0
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if self.properties['sw_wr']:
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self.rtl_header.append(
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self.process_yaml(
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Register.templ_dict['write_wire_assign'],
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{'path': x[0],
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'addr': x[1],
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'genvars': self.genvars_str,
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'genvars_sum': self.genvars_sum_str,
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'depth': self.depth,
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}
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)
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)
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else:
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self.rtl_header.append(
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self.process_yaml(
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Register.templ_dict['write_wire_assign_0'],
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{'path': x[0],
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'genvars': self.genvars_str,
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}
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)
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)
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# Add combined signal to be used for general access of the register
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if self.properties['swacc']:
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self.rtl_header.append(
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self.process_yaml(
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Register.templ_dict['rw_wire_assign_any_alias'],
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{'path': self.name_addr_mappings[0][0],
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'genvars': self.genvars_str,
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'sw_rds_w_genvars': ' || '.join(
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[''.join([x[0], '_sw_rd', self.genvars_str])
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for x in self.name_addr_mappings]),
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'sw_wrs_w_genvars': ' || '.join(
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[''.join([x[0], '_sw_wr', self.genvars_str])
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for x in self.name_addr_mappings])
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}
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)
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)
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def __add_signal_instantiations(self):
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# Add wire/register instantiations
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self.rtl_header = [
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*self.get_signal_instantiations_list(),
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'',
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*self.rtl_header
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]
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def get_signal_instantiations_list(self):
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dict_list = [(key, value) for (key, value) in self.get_signals().items()]
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signal_width = min(max([len(value[0]) for (_, value) in dict_list]), 40)
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name_width = min(max([len(key) for (key, _) in dict_list]), 40)
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return [Register.templ_dict['signal_declaration'].format(
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name = key,
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type = value[0],
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signal_width = signal_width,
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name_width = name_width,
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unpacked_dim = '[{}]'.format(
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']['.join(
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[str(y) for y in value[1]]))
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if value[1] else '')
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for (key, value) in dict_list]
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def add_alias(self, obj: node.RegNode):
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for field in obj.fields():
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# Use range to save field in an array. Reason is, names are allowed to
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# change when using an alias
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field_range = ':'.join(map(str, [field.msb, field.lsb]))
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try:
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self.children[field_range].add_sw_access(field, alias=True)
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except KeyError:
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self.logger.fatal("Range of field '{}' in alias register '{}' does "
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"not correspond to range of field in original "
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"register '{}'. This is illegal according to 10.5.1 b)"
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"of the SystemRDL 2.0 LRM.". format(
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field.inst_name,
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obj.inst_name,
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self.name))
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sys.exit(1)
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# Add name to list
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self.obj.current_idx = [0]
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self.name_addr_mappings.append(
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(self.create_underscored_path_static(obj)[3], obj.absolute_address))
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def __process_variables(
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self,
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obj: node.RegNode,
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parents_dimensions: list,
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parents_stride: list,
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glbl_settings: dict):
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# Save name
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self.obj.current_idx = [0]
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self.name = obj.inst_name
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# Save global settings
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self.glbl_settings = glbl_settings
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# Create mapping between (alias-) name and address
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self.name_addr_mappings = [
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(self.create_underscored_path_static(obj)[3], obj.absolute_address)
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]
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# Geneate already started?
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self.generate_active = glbl_settings['generate_active']
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# Empty array for mux-input signals
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self.sw_mux_assignment_var_name = []
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# Determine dimensions of register
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if obj.is_array:
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self.sel_arr = 'array'
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self.total_array_dimensions = [*parents_dimensions, *self.obj.array_dimensions]
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self.array_dimensions = self.obj.array_dimensions
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# Merge parent's stride with stride of this regfile. Before doing so, the
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|
# respective stride of the different dimensions shall be calculated
|
|
self.total_stride = [
|
|
*parents_stride,
|
|
*[math.prod(self.array_dimensions[i+1:])
|
|
*self.obj.array_stride
|
|
for i, _ in enumerate(self.array_dimensions)]
|
|
]
|
|
else:
|
|
self.sel_arr = 'single'
|
|
self.total_array_dimensions = parents_dimensions
|
|
self.array_dimensions = []
|
|
self.total_stride = parents_stride
|
|
|
|
# How many dimensions were already part of some higher up hierarchy?
|
|
self.parents_depths = len(parents_dimensions)
|
|
|
|
self.total_depth = '[{}]'.format(']['.join(f"{i}" for i in self.total_array_dimensions))
|
|
self.total_dimensions = len(self.total_array_dimensions)
|
|
|
|
self.depth = '[{}]'.format(']['.join(f"{i}" for i in self.array_dimensions))
|
|
self.dimensions = len(self.array_dimensions)
|
|
|
|
# Calculate how many genvars shall be added
|
|
genvars = ['[gv_{}]'.format(chr(97+i)) for i in range(self.total_dimensions)]
|
|
self.genvars_str = ''.join(genvars)
|
|
|
|
# Determine value to compare address with
|
|
genvars_sum = []
|
|
genvars_sum_vectorized = []
|
|
try:
|
|
for i, stride in enumerate(self.total_stride):
|
|
genvars_sum.append(''.join(['gv_', chr(97+i)]))
|
|
genvars_sum.append("*")
|
|
genvars_sum.append(str(stride))
|
|
genvars_sum.append("+")
|
|
|
|
genvars_sum_vectorized.append('vec[')
|
|
genvars_sum_vectorized.append(str(i))
|
|
genvars_sum_vectorized.append(']*')
|
|
genvars_sum_vectorized.append(str(stride))
|
|
genvars_sum_vectorized.append("+")
|
|
|
|
genvars_sum.pop()
|
|
genvars_sum_vectorized.pop()
|
|
|
|
self.logger.debug(
|
|
"Multidimensional with dimensions '{}' and stride '{}'".format(
|
|
self.total_array_dimensions,
|
|
self.total_stride))
|
|
except TypeError:
|
|
self.logger.debug(
|
|
"Caught expected TypeError because self.total_stride is empty")
|
|
except IndexError:
|
|
self.logger.debug(
|
|
"Caugt expected IndexError because genvars_sum is empty")
|
|
|
|
self.genvars_sum_str = ''.join(genvars_sum)
|
|
self.genvars_sum_str_vectorized = ''.join(genvars_sum_vectorized)
|
|
|
|
def get_regwidth(self) -> int:
|
|
return self.obj.get_property('regwidth')
|
|
|