29 Commits

Author	SHA1	Message	Date
Dennis	6e355c62af	Add support for rsvdset and rsvdsetX	2021-10-14 23:16:30 -07:00
Dennis	694f7c124e	Make stickybit available for non-intr fields and add support for sticky	2021-10-03 15:48:27 -07:00
Dennis	f30dce67c2	Give all genvars an gv_ prefix to prevent collisions	2021-10-02 00:38:31 -07:00
Dennis	dc37c87944	Ensure that sw_rd/sw_wr wires are only generated if they are required	2021-10-02 00:32:04 -07:00
Dennis	d3bfdeb3f0	Buswidth is now variable, based on widest register ... Fixes #2.	2021-09-26 21:16:49 -07:00
Dennis	c52e59abd0	Add basic interrupt framework ... Up to this point, interrupt outputs are generated and intr, enable, mask, haltenable, and haltmask are supported. stick, stikcybit and the different types of interrupts are not yet supported. This commit also removes the option to turn off santiy checking. This is a bad idea anyway...	2021-09-25 20:49:39 -07:00
Dennis	28edf17a1c	Pull assignment of multiplexer wires into generate for-loop	2021-09-19 23:24:59 -07:00
Dennis	b89bf3663f	Fix issue with read-mux assignment for multidimensional registers	2021-09-12 16:44:37 -07:00
Dennis	24d5534037	Add support for external registers ... Every single field and every single alias (!) has its own interface to the surrounding hardware. This is required to give users the maximum amount of freedom when defining certain properties in RDL.	2021-09-06 18:48:37 -07:00
Dennis	4f2ac8868a	Rename regs.yaml to register.yaml for consistency reasons	2021-09-06 00:29:29 -07:00
Dennis	c689190080	Add proper support for rdy & error indication in read multiplexer ... The error indication is generated if: - A non-existent register gets read - An existent register gets read but not a single bit can be succesfully read or written. As soon as 1 bit succeeds don't return an error.	2021-09-06 00:26:08 -07:00
Dennis	08b7de9544	Fix read-multiplexer bug in case a reg is _not_ an array	2021-08-22 21:43:53 -07:00
Dennis	2e22d82146	Add swmod and swacc properties and fix field-range bug	2021-06-27 00:09:28 +02:00
Dennis	c7f571b909	Fix missing multiplexer entries for single-dimension registers	2021-06-25 11:45:47 +02:00
Dennis	ce4782c11d	Pull declaration of variables outside of generate scope ... This ensures that code is compilation clean again. Prior to this change, the multiplexer was reading from variables that were declared inside of generate-scopes. Furthermore, a small bug regarding the dimension detection of registers was fixed. If a register wasn't multidimensional itself, but its parent is, the multidimensionalness wasn't detected.	2021-06-25 01:20:32 +02:00
Dennis	32c6fc3c4a	Add read-multiplexer logic ... Evaluating every single wire is maybe not the best way to do this, but it is probably better than writing a very exotic SV construct with (for-)loops, breaks, and a lot of conditions. Most synthesis tools are pretty good at recognizing this case-construct and generating a good mutliplexer.	2021-06-23 01:03:11 +02:00
Dennis	b2c756af41	Add support for alias registers ... This required some fundamental changes. One of them is that YAML fields are now processed in a more systematic way in which all fields are passed via a dictionary. That way, some of the fields are not bound to the original object anymore.	2021-06-12 01:28:29 +02:00
Dennis	5d76830931	Fix generate/endgenerate and end of generate loops in regfiles ... Previously, the beginning of a new loop always caused a new generate keyword, which is wrong.	2021-06-03 12:15:27 +02:00
Dennis	8a82d37737	Add regfile capabilities ... Apart from adding regfiles in general (which is mostly a combination of addrmap and register code), the stride/array_dimension code had to be revisted to be correct for multi dimensional arrays with multi dimensional registers. Lastly, the logger instantiation has been moved to the __init__() method of `Component`.	2021-05-31 00:37:41 +02:00
Dennis	2a3cc9505e	Add support for field_reset and cpuif_reset ... These two special kind of resets are now recognized by the compiler and are propagated to all regfiles, registers, and fields. Furthermore, every object has a set of resets which will be used to generate a seperate input section for resets in the addrmap.	2021-05-24 14:42:24 +02:00
Dennis	b7c1a12179	Add support for enumeration encoding ... Fields that are encoded as enumerations are now recognized by the application. All relevant information will be saved in the Field Object and the variables and I/O list will be generated accordingly. This commit also adds dynamic padding of the I/O and variable lists. Still lacking is the automatic generation of SV packages.	2021-05-24 11:41:45 +02:00
Dennis	085e2ea2dc	Provide more advanced way of adding internal signals or ports ... Now, every snippet of RTL in the YAML file can also hold internal variables (i.e., signals), input or output ports. Furthermore, the input/output port lists are replaced by a dictionary to prevent duplicate entries.	2021-05-23 17:46:48 +02:00
Dennis	c5755bf104	Removed genvars in case only 1 dimension with 1 entry is used	2021-05-17 00:15:43 +02:00
Dennis	3acd7516d3	Fix bug in <REG>_sw_wr/<REG>_sw_rd for non-array registers ... In case a register isn't instantiated as an array, the stride value the compiler returns is set to 'None'. The RTL generator should translate it to '0' (since it doesn't matter anyway).	2021-05-16 12:24:52 +02:00
Dennis	7c4f681241	Add SW read- and write wires, including assignment	2021-05-15 18:00:22 +02:00
Dennis	4738cbfe6c	Add support for 1 packed and 26 unpacked dimensions in addrmap's I/O	2021-05-15 01:17:06 +02:00
Dennis	cecb73f07a	Fundamental changes to the architecture of component classes ... All components (e.g., fields, registers, addrmaps) are now children of a common class Component. This common class has certain common methods such as get_ports(), get_rtl(), or create_logger(). The AddrMap is now prepared to support alias registers by saving the registers in a dictionary. That way, registers can easily be accessed once an alias to a register is found. Furthermore, the addrmap template is now also loaded from a YAML file. Lastly, the first preparements to insert ports into the addrmap module are made. For templates, the indents do not need to be added anymore to the template. Now, a seperate method will automatically indent the RTL based on simple rules (e.g., increment indent if `begin` is found). The CLI also supports settings for the tabs (i.e., real tabs or spaces and the tab width). A lot of functionality from the __init__() method of the field class got reorganized. More logic will be reorganized in the future.	2021-05-15 00:29:59 +02:00
Dennis	59b91536ed	Propgate logger through components and let top-level write SV ... Previously, the SystemVerilog was simply written to the shell. This started to become too long to be readable. Now, the application dumps everything to the output directory that is defined on the command line (or the default). Temporary workaround: the AddrMap component's RTL is completely overwritten by the Register's RTL. This is temporary until the AddrMap also uses a YAML file.	2021-05-11 00:28:52 +02:00
Dennis	861a020aff	Initial commit of SRDL2SV ... The compiler in this commit is still useless and only contains a very rough skeleton of the code. SRDL2SV is only able to create a simple register with hw=rw/sw=rw fields.	2021-05-02 00:58:43 +02:00