Dennis/srdl2sv
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Description
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asicfpgahardware-description-languagehdlrdlregister-description-languageregisterssystemrdlsystemrdl-compilersystemverilogverilog
GPL-3.0 713 KiB
Languages
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%