Dennis/srdl2sv
1
0
Fork 0
mirror of https://github.com/Silicon1602/srdl2sv.git synced 2024-11-13 02:53:37 +00:00
Code Issues Projects Releases Wiki Activity
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
3 Commits 1 Branch 0 Tags 713 KiB
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%
ea998b7db0
Go to file
Dennis ea998b7db0
Add argparse.ArgumentParser based CliArguments class 
This wrapper lives in a seperate module and class so that possible
processing of arguments can be done before the config dictionary
gets passed to the compiler.
2021-05-08 11:17:56 +02:00
srdl2sv Add argparse.ArgumentParser based CliArguments class 2021-05-08 11:17:56 +02:00
.gitignore Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00
LIMITATIONS.md Initial commit of SRDL2SV 2021-05-02 00:58:43 +02:00