mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-12-22 06:58:41 +00:00
Add swwe and swwel properties
Note: swwe=True & swwel=True are not yet supported (since they don't really make sense). At this point, references are (partly) supported.
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parent
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commit
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@ -1,6 +1,7 @@
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import re
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from itertools import chain
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from typing import NamedTuple
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from systemrdl import node
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# Local modules
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from log.log import create_logger
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@ -91,3 +92,41 @@ class Component():
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indent_lvl += 1
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return '\n'.join(rtl_indented)
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@staticmethod
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def get_underscored_path(path: str, owning_addrmap: str):
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return path\
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.replace('[]', '')\
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.replace('{}.'.format(owning_addrmap), '')\
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.replace('.', '_')
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@staticmethod
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def split_dimensions(path: str):
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new_path = re.match(r'(.*?)(\[.*\])?(.*)', path)
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return (''.join([new_path.group(1), new_path.group(3)]),
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new_path.group(2) if new_path.group(2) else '[0]')
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@staticmethod
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def get_ref_name(obj):
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name = []
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split_name = Component.split_dimensions(
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Component.get_underscored_path(
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obj.get_path(),
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obj.owning_addrmap.inst_name)
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)
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name.append(split_name[0])
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if isinstance(obj, (node.FieldNode)):
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name.append('_q')
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name.append(split_name[1])
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return ''.join(name)
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@ -16,7 +16,7 @@ class Field(Component):
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pkg_resources.read_text(templates, 'fields.yaml'),
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Loader=yaml.FullLoader)
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def __init__(self, obj: node.RootNode, dimensions: list, config:dict):
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def __init__(self, obj: node.FieldNode, dimensions: list, config:dict):
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super().__init__()
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# Save and/or process important variables
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@ -208,6 +208,22 @@ class Field(Component):
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access_rtl['sw_write'] = []
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if self.sw_access in (AccessType.rw, AccessType.w):
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swwe = self.obj.get_property('swwe')
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swwel = self.obj.get_property('swwel')
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if isinstance(swwe, (node.FieldNode, node.SignalNode)):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field_swwe'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str,
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swwe = Component.get_ref_name(swwe)))
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elif isinstance(swwel, (node.FieldNode, node.SignalNode)):
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field_swwel'].format(
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path_wo_field = self.path_wo_field,
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genvars = self.genvars_str,
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swwel = Component.get_ref_name(swwel)))
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else:
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access_rtl['sw_write'].append(
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Field.templ_dict['sw_access_field'].format(
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path_wo_field = self.path_wo_field,
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@ -12,6 +12,12 @@ rst_field_assign: |-
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sw_access_field: |-
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if ({path_wo_field}_sw_wr{genvars})
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begin
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sw_access_field_swwe: |-
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if ({path_wo_field}_sw_wr{genvars} && {swwe}) // swwe property
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begin
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sw_access_field_swwel: |-
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if ({path_wo_field}_sw_wr{genvars} && !{swwel}) // swwel property
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begin
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sw_access_byte: |-
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if (byte_enable[{i}])
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begin
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