mirror of
https://github.com/Silicon1602/srdl2sv.git
synced 2024-11-14 03:03:35 +00:00
Add swwe and swwel properties
Note: swwe=True & swwel=True are not yet supported (since they don't really make sense). At this point, references are (partly) supported.
This commit is contained in:
parent
92d61dd7c8
commit
203f1e1b36
@ -1,6 +1,7 @@
|
||||
import re
|
||||
from itertools import chain
|
||||
from typing import NamedTuple
|
||||
from systemrdl import node
|
||||
|
||||
# Local modules
|
||||
from log.log import create_logger
|
||||
@ -91,3 +92,41 @@ class Component():
|
||||
indent_lvl += 1
|
||||
|
||||
return '\n'.join(rtl_indented)
|
||||
|
||||
@staticmethod
|
||||
def get_underscored_path(path: str, owning_addrmap: str):
|
||||
return path\
|
||||
.replace('[]', '')\
|
||||
.replace('{}.'.format(owning_addrmap), '')\
|
||||
.replace('.', '_')
|
||||
|
||||
@staticmethod
|
||||
def split_dimensions(path: str):
|
||||
new_path = re.match(r'(.*?)(\[.*\])?(.*)', path)
|
||||
return (''.join([new_path.group(1), new_path.group(3)]),
|
||||
new_path.group(2) if new_path.group(2) else '[0]')
|
||||
|
||||
@staticmethod
|
||||
def get_ref_name(obj):
|
||||
name = []
|
||||
|
||||
split_name = Component.split_dimensions(
|
||||
Component.get_underscored_path(
|
||||
obj.get_path(),
|
||||
obj.owning_addrmap.inst_name)
|
||||
)
|
||||
|
||||
name.append(split_name[0])
|
||||
|
||||
if isinstance(obj, (node.FieldNode)):
|
||||
name.append('_q')
|
||||
|
||||
name.append(split_name[1])
|
||||
|
||||
return ''.join(name)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
@ -16,7 +16,7 @@ class Field(Component):
|
||||
pkg_resources.read_text(templates, 'fields.yaml'),
|
||||
Loader=yaml.FullLoader)
|
||||
|
||||
def __init__(self, obj: node.RootNode, dimensions: list, config:dict):
|
||||
def __init__(self, obj: node.FieldNode, dimensions: list, config:dict):
|
||||
super().__init__()
|
||||
|
||||
# Save and/or process important variables
|
||||
@ -208,10 +208,26 @@ class Field(Component):
|
||||
access_rtl['sw_write'] = []
|
||||
|
||||
if self.sw_access in (AccessType.rw, AccessType.w):
|
||||
access_rtl['sw_write'].append(
|
||||
Field.templ_dict['sw_access_field'].format(
|
||||
path_wo_field = self.path_wo_field,
|
||||
genvars = self.genvars_str))
|
||||
swwe = self.obj.get_property('swwe')
|
||||
swwel = self.obj.get_property('swwel')
|
||||
|
||||
if isinstance(swwe, (node.FieldNode, node.SignalNode)):
|
||||
access_rtl['sw_write'].append(
|
||||
Field.templ_dict['sw_access_field_swwe'].format(
|
||||
path_wo_field = self.path_wo_field,
|
||||
genvars = self.genvars_str,
|
||||
swwe = Component.get_ref_name(swwe)))
|
||||
elif isinstance(swwel, (node.FieldNode, node.SignalNode)):
|
||||
access_rtl['sw_write'].append(
|
||||
Field.templ_dict['sw_access_field_swwel'].format(
|
||||
path_wo_field = self.path_wo_field,
|
||||
genvars = self.genvars_str,
|
||||
swwel = Component.get_ref_name(swwel)))
|
||||
else:
|
||||
access_rtl['sw_write'].append(
|
||||
Field.templ_dict['sw_access_field'].format(
|
||||
path_wo_field = self.path_wo_field,
|
||||
genvars = self.genvars_str))
|
||||
|
||||
# Check if an onwrite property is set
|
||||
onwrite = self.obj.get_property('onwrite')
|
||||
|
@ -12,6 +12,12 @@ rst_field_assign: |-
|
||||
sw_access_field: |-
|
||||
if ({path_wo_field}_sw_wr{genvars})
|
||||
begin
|
||||
sw_access_field_swwe: |-
|
||||
if ({path_wo_field}_sw_wr{genvars} && {swwe}) // swwe property
|
||||
begin
|
||||
sw_access_field_swwel: |-
|
||||
if ({path_wo_field}_sw_wr{genvars} && !{swwel}) // swwel property
|
||||
begin
|
||||
sw_access_byte: |-
|
||||
if (byte_enable[{i}])
|
||||
begin
|
||||
|
Loading…
Reference in New Issue
Block a user