Closes #4: Add support for hierarchical addrmaps

Every time an addrmap is detected within another addrmap, a new context
will be opened and a separate RTL file will be created.

All addrmaps will have the same bus-wdiget, but it might be possible
that different addrmaps have different maximum regwidths. For that
reason, it was necessary to change the non-generic srd2sv_if_pkg to a
parametrizable interface.

Almost all changes to the templates in this commit are due to name
changes from 'b2r' and 'r2b' to 'widget_if'.

srdl2sv/components/addrmap.py

@@ -30,6 +30,9 @@ class AddrMap(Component):
                     parents_strides=None,
                     parents_dimensions=None)
 
+        # Name of addrmap should always be the object's name and not the name of the instance
+        self.name = obj.type_name
+
         # Check if global resets are defined
         glbl_settings = {}
 
@@ -47,6 +50,8 @@ class AddrMap(Component):
         # Empty dictionary of register objects
         # We need a dictionary since it might be required to access the objects later
         # by name (for example, in case of aliases)
+        self.addrmap_ids = {}
+        self.addrmaps = []
         self.registers = {}
         self.regfiles = {}
         self.mems = {}
@@ -54,12 +59,34 @@ class AddrMap(Component):
 
         # Traverse through children
         for child in self.obj.children():
-            print(child)
+            new_child = None
+
             if isinstance(child, node.AddrmapNode):
                 # This addressmap opens a completely new scope. For example,
                 # a field_reset does not propagate through to this scope.
-                self.logger.info('Found hierarchical addrmap. Entering it...')
+                #
-                self.logger.error('Child addrmaps are not implemented yet!')
+                # We only need to create files for objects, not for instantiations.
+                # For that reason, scan if we already created an instance of this
+                # object. 
+                if child.type_name not in self.addrmap_ids:
+                    self.logger.info("Found hierarchical addrmap of type '%s' " \
+                                     ". Entering it...", child.type_name)
+
+                    # Save unique ID of object to dictionary
+                    self.addrmap_ids[child.type_name] = id(child.inst.original_def)
+
+                    # Create addrmap object
+                    self.addrmaps.append(AddrMap(obj=child, config=config))
+                elif id(child.inst.original_def) == self.addrmap_ids[child.type_name]:
+                    self.logger.info("Found another instance of addrmap '%s'. " \
+                                     "Not rebuilding it...", child.type_name)
+                else:
+                    self.logger.fatal("Found a redeclaration of addrmap '%s'. " \
+                                      "This is not supported by srdl2sv because " \
+                                      "the compiler will create a seperate SystemVerilog " \
+                                      "module for every addrmap object.", child.type_name)
+
+                    sys.exit(1)
             elif isinstance(child, node.RegfileNode):
                 new_child = RegFile(
                                 obj=child,
@@ -77,7 +104,6 @@ class AddrMap(Component):
                 new_child.sanity_checks()
                 self.mems[child.inst_name] = new_child
             elif isinstance(child, node.RegNode):
-                print('here')
                 if child.inst.is_alias:
                     # If the node we found is an alias, we shall not create a
                     # new register. Rather, we bury up the old register and add
@@ -96,7 +122,7 @@ class AddrMap(Component):
             try:
                 if (regwidth := new_child.get_regwidth()) > self.regwidth:
                     self.regwidth = regwidth
-            except (KeyError, UnboundLocalError):
+            except (KeyError, UnboundLocalError, AttributeError):
                 # Simply ignore nodes like SignalNodes
                 pass
 
@@ -178,11 +204,7 @@ class AddrMap(Component):
 
         # Define packages to be included. Always include the
         # b2w and w2b defines.
-        import_package_list = [
+        import_package_list = []
-            AddrMap.templ_dict['import_package']['rtl'].format(
-                name = 'srdl2sv_if'),
-            '\n'
-            ]
 
         try:
             for pkg_name in self.__get_package_names():
@@ -195,7 +217,11 @@ class AddrMap(Component):
         except IndexError:
             pass
 
+        try:
             import_package_list.pop()
+        except IndexError:
+            # If there are no packages, an IndexError is expected
+            pass
 
         self.rtl_header.append(
             AddrMap.templ_dict['header'].format(
@@ -243,17 +269,17 @@ class AddrMap(Component):
         for child in self.children.values():
             for mux_entry_dim in child.create_mux_string():
                 # Data structure of mux_entry:
-                r2b_data = ''.join([mux_entry_dim.mux_entry.data_wire, mux_entry_dim.dim])
+                widget_if_r_data = ''.join([mux_entry_dim.mux_entry.data_wire, mux_entry_dim.dim])
-                r2b_rdy = ''.join([mux_entry_dim.mux_entry.rdy_wire, mux_entry_dim.dim])
+                widget_if_rdy = ''.join([mux_entry_dim.mux_entry.rdy_wire, mux_entry_dim.dim])
-                r2b_err = ''.join([mux_entry_dim.mux_entry.err_wire, mux_entry_dim.dim])
+                widget_if_err = ''.join([mux_entry_dim.mux_entry.err_wire, mux_entry_dim.dim])
                 active_wire = ''.join([mux_entry_dim.mux_entry.active_wire, mux_entry_dim.dim])
 
                 list_of_cases.append(
                     AddrMap.templ_dict['list_of_mux_cases']['rtl'].format(
                         active_wire = active_wire,
-                        r2b_data = r2b_data,
+                        widget_if_r_data = widget_if_r_data,
-                        r2b_rdy = r2b_rdy,
+                        widget_if_rdy = widget_if_rdy,
-                        r2b_err = r2b_err)
+                        widget_if_err = widget_if_err)
                     )
 
         # Define default case
@@ -410,3 +436,8 @@ class AddrMap(Component):
                 real_tabs)
 
         return rtl_return
+
+    def get_addrmaps(self) -> []:
+        self.logger.debug("Returning addrmaps")
+
+        return [self, *[y for x in self.addrmaps for y in x.get_addrmaps()]]

srdl2sv/components/register.py

@@ -215,8 +215,8 @@ class Register(Component):
             # an error.
             #
             # Furthermore, consider an error indication that is set for external registers
-            bytes_read_format = [f"b2r.byte_en[{x}]" for x in list(map(str, bytes_read))]
+            bytes_read_format = [f"widget_if.byte_en[{x}]" for x in list(map(str, bytes_read))]
-            bytes_written_format = [f"b2r.byte_en[{x}]" for x in list(map(str, bytes_written))]
+            bytes_written_format = [f"widget_if.byte_en[{x}]" for x in list(map(str, bytes_written))]
 
             sw_err_condition_vec = []
 
@@ -270,7 +270,7 @@ class Register(Component):
                         sw_rdy_condition_vec.append(' && ')
 
                     sw_rdy_condition_vec.pop()
-                    sw_rdy_condition_vec.append(' && b2r.r_vld)')
+                    sw_rdy_condition_vec.append(' && widget_if.r_vld)')
 
                 if bytes_read and bytes_written:
                     sw_rdy_condition_vec.append(' || ')
@@ -290,7 +290,7 @@ class Register(Component):
                         sw_rdy_condition_vec.append(' && ')
 
                     sw_rdy_condition_vec.pop()
-                    sw_rdy_condition_vec.append(' && b2r.w_vld)')
+                    sw_rdy_condition_vec.append(' && widget_if.w_vld)')
 
                 sw_rdy_condition = ''.join(sw_rdy_condition_vec)
             else:

srdl2sv/components/templates/addrmap.yaml

@@ -129,15 +129,15 @@ default_mux_case:
         default:
         begin
         // If the address is not found, return an error
-        r2b.data = 0;
+        widget_if.r_data = 0;
-        r2b.err  = 1;
+        widget_if.err    = 1;
-        r2b.rdy  = b2r.r_vld || b2r.w_vld;
+        widget_if.rdy    = widget_if.r_vld || widget_if.w_vld;
         end
 list_of_mux_cases:
     rtl: |-
         {active_wire}:
         begin
-        r2b.data = {r2b_data};
+        widget_if.r_data = {widget_if_r_data};
-        r2b.err  = {r2b_err};
+        widget_if.err    = {widget_if_err};
-        r2b.rdy  = {r2b_rdy};
+        widget_if.rdy    = {widget_if_rdy};
         end

srdl2sv/components/templates/fields.yaml

@@ -29,9 +29,9 @@ sw_access_field_swwel:
         begin
 sw_access_byte: 
     rtl: |-
-        if (b2r.byte_en[{i}])
+        if (widget_if.byte_en[{i}])
         <<INDENT>>
-        {path}_q{genvars}[{msb_field}:{lsb_field}] <= b2r.data[{msb_bus}:{lsb_bus}];
+        {path}_q{genvars}[{msb_field}:{lsb_field}] <= widget_if.w_data[{msb_bus}:{lsb_bus}];
         <<UNINDENT>>
     signals:
         - name: '{path}_q'
@@ -113,33 +113,33 @@ end_field_ff:
         end // of {path}'s always_ff
 OnWriteType.woset: 
     rtl: |-
-        if (b2r.byte_en[{i}]) // woset property
+        if (widget_if.byte_en[{i}]) // woset property
         begin
-        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] | b2r.data[{msb_bus}:{lsb_bus}];
+        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] | widget_if.w_data[{msb_bus}:{lsb_bus}];
         end
 OnWriteType.woclr: 
     rtl: |-
-        if (b2r.byte_en[{i}]) // woclr property
+        if (widget_if.byte_en[{i}]) // woclr property
         begin
-        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] & ~b2r.data[{msb_bus}:{lsb_bus}];
+        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] & ~widget_if.w_data[{msb_bus}:{lsb_bus}];
         end
 OnWriteType.wot: 
     rtl: |-
-        if (b2r.byte_en[{i}]) // wot property
+        if (widget_if.byte_en[{i}]) // wot property
         begin
-        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] ^ b2r.data[{msb_bus}:{lsb_bus}];
+        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] ^ widget_if.w_data[{msb_bus}:{lsb_bus}];
         end
 OnWriteType.wzs: 
     rtl: |-
-        if (b2r.byte_en[{i}]) // wzs property
+        if (widget_if.byte_en[{i}]) // wzs property
         begin
-        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] & b2r.data[{msb_bus}:{lsb_bus}];
+        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] & widget_if.w_data[{msb_bus}:{lsb_bus}];
         end
 OnWriteType.wzt: 
     rtl: |-
-        if (b2r.byte_en[{i}]) // wzt property
+        if (widget_if.byte_en[{i}]) // wzt property
         begin
-        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] ~^ b2r.data[{msb_bus}:{lsb_bus}];
+        {path}_q{genvars}[{msb_field}:{lsb_field}] <= {path}_q{genvars}[{msb_field}:{lsb_field}] ~^ widget_if.w_data[{msb_bus}:{lsb_bus}];
         end
 OnWriteType.wclr: 
     rtl: |-
@@ -216,7 +216,7 @@ swacc_assign:
     rtl: |-
 
         // Combinational block to generate swacc-output signals
-        assign {path}_swacc{genvars} = ({path_wo_field}__any_alias_sw_wr{genvars} || {path_wo_field}__any_alias_sw_rd{genvars}) && |b2r.byte_en[{msbyte}:{lsbyte}];
+        assign {path}_swacc{genvars} = ({path_wo_field}__any_alias_sw_wr{genvars} || {path_wo_field}__any_alias_sw_rd{genvars}) && |widget_if.byte_en[{msbyte}:{lsbyte}];
     output_ports:
         - name: '{path}_swacc'
           signal_type: 'logic'
@@ -234,7 +234,7 @@ swmod_always_comb:
           signal_type: 'logic'
 swmod_assign: 
     rtl: |-
-        {path}_swmod{genvars} |= {path_wo_field}__any_alias_sw_{rd_wr}{genvars} && |b2r.byte_en[{msbyte}:{lsbyte}];
+        {path}_swmod{genvars} |= {path_wo_field}__any_alias_sw_{rd_wr}{genvars} && |widget_if.byte_en[{msbyte}:{lsbyte}];
     output_ports:
         - name: '{path}_swmod'
           signal_type: 'logic'
@@ -454,7 +454,7 @@ external_wr_assignments:
         assign {path}_ext_w_req{genvars} = {path_wo_field}_sw_wr{genvars};
 
         // Assign value from bus to output
-        assign {path}_ext_w_data{genvars} = b2r.data[{msb_bus}:{lsb_bus}];
+        assign {path}_ext_w_data{genvars} = widget_if.w_data[{msb_bus}:{lsb_bus}];
 
         // Provide bit-wise mask. Only bits set to 1'b1 shall be written
         assign {path}_ext_w_mask{genvars} = {{{mask}}};
@@ -472,7 +472,7 @@ external_wr_assignments:
           signal_type: ''
 external_wr_mask_segment:
     rtl: |-
-        {{{width}{{b2r.byte_en[{idx}]}}}}
+        {{{width}{{widget_if.byte_en[{idx}]}}}}
 trigger_input:
     rtl: |-
         {path}_in

srdl2sv/components/templates/memory.yaml

@@ -36,7 +36,7 @@ memory_adr_assignments:
          * The address is divided so that byte-addresses are
          * translated full memory entries
          */
-        assign {path}_mem_address = (b2r.addr - {lower_bound}) / {bytes_w};
+        assign {path}_mem_address = (widget_if.addr - {lower_bound}) / {bytes_w};
         assign {path}_mem_active = {path}_mem_address >= {lower_bound} && {path}_mem_address < {upper_bound};
 
     signals:
@@ -65,7 +65,7 @@ memory_rd_assignments:
          * complete time '{path}_mem_r_ack' is high.
          */
         // Request read signal
-        assign {path}_mem_r_req = {path}_mem_active && b2r.r_vld;
+        assign {path}_mem_r_req = {path}_mem_active && widget_if.r_vld;
     input_ports:
         - name: '{path}_mem_r_data'
           signal_type: '[{data_w}:0]'
@@ -99,10 +99,10 @@ memory_wr_assignments:
          * complete time '{path}_mem_w_ack' is high.
          */
         // Write request
-        assign {path}_mem_w_req = {path}_mem_active && b2r.w_vld;
+        assign {path}_mem_w_req = {path}_mem_active && widget_if.w_vld;
 
         // Assign value from bus to output
-        assign {path}_mem_w_data = b2r.data;
+        assign {path}_mem_w_data = widget_if.w_data;
     output_ports:
         - name: '{path}_mem_w_req'
           signal_type: 'logic'

srdl2sv/components/templates/register.yaml

@@ -5,19 +5,19 @@ access_wire_comment:
         // Register-activation for '{path}' {alias}
 access_wire_assign_1_dim:
     rtl: |-
-        assign {path}_active = b2r.addr == {addr};
+        assign {path}_active = widget_if.addr == {addr};
     signals:
         - name: '{path}_active'
           signal_type: 'logic'
 access_wire_assign_multi_dim:
     rtl: |-
-        assign {path}_active{genvars} = b2r.addr == {addr}+({genvars_sum});
+        assign {path}_active{genvars} = widget_if.addr == {addr}+({genvars_sum});
     signals:
         - name: '{path}_active'
           signal_type: 'logic'
 read_wire_assign: 
     rtl: |-
-        assign {path}_sw_rd{genvars} = {path}_active{genvars} && b2r.r_vld;
+        assign {path}_sw_rd{genvars} = {path}_active{genvars} && widget_if.r_vld;
     signals:
         - name: '{path}_sw_rd'
           signal_type: 'logic'
@@ -29,7 +29,7 @@ read_wire_assign_0:
           signal_type: 'logic'
 write_wire_assign: 
     rtl: |-
-        assign {path}_sw_wr{genvars} = {path}_active{genvars} && b2r.w_vld;
+        assign {path}_sw_wr{genvars} = {path}_active{genvars} && widget_if.w_vld;
     signals:
         - name: '{path}_sw_wr'
           signal_type: 'logic'
@@ -92,7 +92,7 @@ sw_rdy_assignment_var_name:
           signal_type: 'logic'
 sw_err_condition:
     rtl: |-
-        !((b2r.r_vld && ({rd_byte_list_ored})) || (b2r.w_vld && ({wr_byte_list_ored})))
+        !((widget_if.r_vld && ({rd_byte_list_ored})) || (widget_if.w_vld && ({wr_byte_list_ored})))
 sw_data_assignment:
     rtl: |-
 
@@ -133,7 +133,7 @@ external_rdy_condition:
           signal_type: 'logic'
 external_err_condition:
     rtl: |-
-        ({path}_ext_{rd_or_wr}_err{genvars} && {path}_ext_{rd_or_wr}_ack{genvars} && b2r.{rd_or_wr}_vld)
+        ({path}_ext_{rd_or_wr}_err{genvars} && {path}_ext_{rd_or_wr}_ack{genvars} && widget_if.{rd_or_wr}_vld)
     input_ports:
         - name: '{path}_ext_{rd_or_wr}_err'
           signal_type: 'logic'

srdl2sv/components/widgets/srdl2sv_amba3ahblite.sv

@@ -23,20 +23,12 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
-module srdl2sv_amba3ahblite
+module srdl2sv_amba3ahblite #(
-    import srdl2sv_if_pkg::*;
-#(
     parameter bit FLOP_REGISTER_IF = 0,
     parameter     BUS_BITS         = 32,
     parameter     NO_BYTE_ENABLE   = 0
 )
 (
-    // Outputs to internal logic
-    output b2r_t                b2r,
-
-    // Inputs from internal logic
-    input  r2b_t                r2b,
- 
     // Bus protocol
     input                       HCLK,
     input                       HRESETn,
@@ -50,7 +42,10 @@ module srdl2sv_amba3ahblite
 
     output logic                HREADYOUT,
     output logic                HRESP,
-    output logic [BUS_BITS-1:0] HRDATA
+    output logic [BUS_BITS-1:0] HRDATA,
+
+    // Interface to internal logic
+    srdl2sv_widget_if.widget    widget_if
 );
 
     localparam BUS_BYTES = BUS_BITS/8;
@@ -145,7 +140,7 @@ module srdl2sv_amba3ahblite
         // When reading back, the data of the bit that was accessed over the bus
         // should be at byte 0 of the HRDATA bus and bits that were not accessed
         // should be masked with 0s.
-        HRDATA_temp = r2b.data >> (8*HADDR_q[BUS_BYTES_W-1:0]);
+        HRDATA_temp = widget_if.r_data >> (8*HADDR_q[BUS_BYTES_W-1:0]);
 
         for (int i = 0; i < BUS_BYTES; i++)
             if (i < (1 << HSIZE_q))
@@ -153,8 +148,8 @@ module srdl2sv_amba3ahblite
             else
                 HRDATA[8*(i+1)-1 -: 8] = 8'b0;
 
-        b2r_w_vld_next = 0;
+        widget_if_w_vld_next = 0;
-        b2r_r_vld_next = 0;
+        widget_if_r_vld_next = 0;
         fsm_next       = fsm_q;
 
         case (fsm_q)
@@ -175,11 +170,11 @@ module srdl2sv_amba3ahblite
             end
             FSM_TRANS:
             begin
-                HREADYOUT = r2b.rdy;
+                HREADYOUT = widget_if.rdy;
-                b2r_w_vld_next = operation_q == WRITE;
+                widget_if_w_vld_next = operation_q == WRITE;
-                b2r_r_vld_next = operation_q == READ;
+                widget_if_r_vld_next = operation_q == READ;
 
-                if (r2b.err && r2b.rdy)
+                if (widget_if.err && widget_if.rdy)
                 begin
                     fsm_next = FSM_ERR_0;
                 end
@@ -201,7 +196,7 @@ module srdl2sv_amba3ahblite
                 else if (HTRANS == IDLE)
                 begin
                     // All done, wrapping things up!
-                    fsm_next = r2b.rdy ? FSM_IDLE : FSM_TRANS;
+                    fsm_next = widget_if.rdy ? FSM_IDLE : FSM_TRANS;
                 end
             end
             FSM_ERR_0:
@@ -253,14 +248,14 @@ module srdl2sv_amba3ahblite
      * Determine the number of active bytes
      ***/
     logic [BUS_BYTES-1:0] HSIZE_bitfielded;
-    logic [BUS_BYTES-1:0] b2r_byte_en_next;
+    logic [BUS_BYTES-1:0] widget_if_byte_en_next;
-    logic                 b2r_w_vld_next;
+    logic                 widget_if_w_vld_next;
-    logic                 b2r_r_vld_next;
+    logic                 widget_if_r_vld_next;
 
     generate
     if (NO_BYTE_ENABLE)
     begin
-        assign b2r_byte_en_next = {BUS_BYTES{1'b1}}; 
+        assign widget_if_byte_en_next = {BUS_BYTES{1'b1}}; 
     end
     else
     begin
@@ -270,7 +265,7 @@ module srdl2sv_amba3ahblite
                 HSIZE_bitfielded[i] = i < (1 << HSIZE_q);
 
             // Shift if not the full bus is accessed
-            b2r_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
+            widget_if_byte_en_next = HSIZE_bitfielded << (HADDR_q % BUS_BYTES);
         end
     end
     endgenerate
@@ -284,29 +279,29 @@ module srdl2sv_amba3ahblite
         always_ff @ (posedge HCLK or negedge HRESETn)
             if (!HRESETn)
             begin
-                b2r.w_vld <= 1'b0;
+                widget_if.w_vld <= 1'b0;
-                b2r.r_vld <= 1'b0;
+                widget_if.r_vld <= 1'b0;
             end
             else
             begin
-                b2r.w_vld <= b2r_w_vld_next;
+                widget_if.w_vld <= widget_if_w_vld_next;
-                b2r.r_vld <= b2r_r_vld_next;
+                widget_if.r_vld <= widget_if_r_vld_next;
             end
 
         always_ff @ (posedge HCLK)
         begin
-            b2r.addr    <= {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
+            widget_if.addr    <= {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
-            b2r.data    <= HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
+            widget_if.w_data  <= HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
-            b2r.byte_en <= b2r_byte_en_next;
+            widget_if.byte_en <= widget_if_byte_en_next;
         end
     end
     else
     begin
-        assign b2r.w_vld   = b2r_w_vld_next;
+        assign widget_if.w_vld   = widget_if_w_vld_next;
-        assign b2r.r_vld   = b2r_r_vld_next;
+        assign widget_if.r_vld   = widget_if_r_vld_next;
-        assign b2r.addr    = {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
+        assign widget_if.addr    = {HADDR_q[31:BUS_BYTES_W], {BUS_BYTES_W{1'b0}}};
-        assign b2r.data    = HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
+        assign widget_if.w_data  = HWDATA << (8*HADDR_q[BUS_BYTES_W-1:0]);
-        assign b2r.byte_en = b2r_byte_en_next;
+        assign widget_if.byte_en = widget_if_byte_en_next;
     end
     endgenerate
 

srdl2sv/components/widgets/srdl2sv_amba3ahblite.yaml

@@ -5,8 +5,8 @@ module_instantiation:
          * AMBA 3 AHB Lite Widget
          * ======================
          * Naming conventions
-         *    - r2b.*     -> Signals from registers to bus
+         *    - widget_if -> SystemVerilog interface to between widgets
-         *    - b2r.*     -> Signals from bus to registers
+         *                   and the internal srdl2sv registers.
          *    - H*        -> Signals as defined in AMBA3 AHB Lite 
          *                   specification
          *    - clk       -> Clock that drives registers and the bus
@@ -16,13 +16,7 @@ module_instantiation:
                .BUS_BITS         ({bus_width}),
                .NO_BYTE_ENABLE   ({no_byte_enable}))
         srdl2sv_amba3ahblite_inst
-             (// Outputs to internal logic
+             (// Bus protocol
-             .b2r,
-
-             // Inputs from internal logic
-             .r2b,
- 
-             // Bus protocol
              .HRESETn,
              .HCLK        (clk),
              .HADDR,
@@ -35,12 +29,14 @@ module_instantiation:
 
              .HREADYOUT,
              .HRESP,
-             .HRDATA);
+             .HRDATA,
+
+             // Interface to internal logic
+             .widget_if);
     signals:
-        - name: 'b2r'
+    signals:
-          signal_type: 'b2r_t'
+        - name: 'widget_if'
-        - name: 'r2b'
+          signal_type: 'srdl2sv_widget_if #(.ADDR_W ({addr_width}), .DATA_W({bus_width}))'
-          signal_type: 'r2b_t'
     input_ports:
         - name: 'clk'
           signal_type: ''

srdl2sv/components/widgets/srdl2sv_if_pkg.sv

@@ -1,17 +0,0 @@
-package srdl2sv_if_pkg;
-
-typedef struct packed {{ // .Verilator does not support unpacked structs in packages
-    logic [{addrwidth}:0] addr;
-    logic [{regwidth_bit}:0] data;
-    logic        w_vld;
-    logic        r_vld;
-    logic [ {regwidth_byte}:0] byte_en;
-}} b2r_t;
-
-typedef struct packed {{ // .Verilator does not support unpacked structs in packages
-    logic [{regwidth_bit}:0] data;
-    logic        rdy;
-    logic        err;
-}} r2b_t;
-
-endpackage

srdl2sv/components/widgets/srdl2sv_simple.yaml

@@ -3,26 +3,19 @@ module_instantiation:
     rtl: |-
         /*******************************************************************
          * CPU Interface
-         * ======================
-         * Naming conventions
-         *    - r2b.*     -> Signals from registers to bus
-         *    - b2r.*     -> Signals from bus to registers
-         *    - clk       -> Clock that drives registers and the bus
          *******************************************************************/
-        assign b2r.addr     = cpuif_address_i;
+        assign widget_if.addr     = cpuif_address_i;
-        assign b2r.data     = cpuif_data_i;
+        assign widget_if.w_data   = cpuif_data_i;
-        assign b2r.w_vld    = cpuif_wr_vld_i;
+        assign widget_if.w_vld    = cpuif_wr_vld_i;
-        assign b2r.r_vld    = cpuif_rd_vld_i;
+        assign widget_if.r_vld    = cpuif_rd_vld_i;
-        assign b2r.byte_en  = {no_byte_enable} ? {{{bus_width_byte}{{1'b1}}}} : cpuif_byte_enable_i;
+        assign widget_if.byte_en  = {no_byte_enable} ? {{{bus_width_byte}{{1'b1}}}} : cpuif_byte_enable_i;
 
-        assign cpuif_data_o = r2b.data; 
+        assign cpuif_data_o = widget_if.r_data; 
-        assign cpuif_rdy_o  = r2b.rdy;
+        assign cpuif_rdy_o  = widget_if.rdy;
-        assign cpuif_err_o  = r2b.err;
+        assign cpuif_err_o  = widget_if.err;
     signals:
-        - name: 'b2r'
+        - name: 'widget_if'
-          signal_type: 'b2r_t'
+          signal_type: 'srdl2sv_widget_if #(.ADDR_W ({addr_width}), .DATA_W({bus_width}). NO_BYTE_ENABLE({no_byte_enable}))'
-        - name: 'r2b'
-          signal_type: 'r2b_t'
     input_ports:
         - name: 'clk'
           signal_type: ''

srdl2sv/components/widgets/srdl2sv_widget_if.sv

@@ -0,0 +1,29 @@
+interface srdl2sv_widget_if #(
+    parameter ADDR_W = 32,
+    parameter DATA_W = 32
+);
+
+    localparam DATA_BYTES = DATA_W >> 3;
+
+    logic [ADDR_W-1:0]      addr;
+    logic [DATA_W-1:0]      w_data;
+    logic                   w_vld;
+    logic                   r_vld;
+    logic [DATA_BYTES-1:0]  byte_en;
+
+    logic [DATA_W-1:0]      r_data;
+    logic                   rdy;
+    logic                   err;
+
+    modport widget (
+        output addr,
+        output w_data,
+        output w_vld,
+        output r_vld,
+        output byte_en,
+
+        input  r_data,
+        input  rdy,
+        input  err
+    );
+endinterface

srdl2sv/components/widgets/widget_package.sv

@@ -1,17 +0,0 @@
-package srdl2sv_widget_pkg;
-
-typedef struct {
-    logic [31:0] addr;
-    logic [31:0] data;
-    logic        w_vld;
-    logic        r_vld;
-    logic [ 3:0] byte_en;
-} b2r_t;
-
-typedef struct {
-    logic [31:0] data;
-    logic        rdy;
-    logic        err;
-} r2b_t;
-
-endpackage

srdl2sv/srdl2sv.py

@@ -44,10 +44,17 @@ def main():
         logger.fatal("Could not find '%s'", input_file)
         sys.exit(1)
 
-    addrmap = AddrMap(root.top, config)
+    addrmaps = AddrMap(root.top, config)
+
+    # Determine address width
+    if config['addrwidth_bus_spec']:
+        logger.info("Set address width to '%i', according to '%s' specification",
+                     config['addrwidth'], config['bus'])
+    else:
+        logger.info("Set address width to '%i'", config['addrwidth'])
 
     # Save RTL to file
-    # Start out with addrmap
+    for addrmap in addrmaps.get_addrmaps():
         out_addrmap_file = f"{config['output_dir']}/{addrmap.name}.sv"
 
         with open(out_addrmap_file, 'w', encoding='UTF-8') as file:
@@ -71,6 +78,16 @@ def main():
                 with open(f"{config['output_dir']}/{key}_pkg.sv", 'w', encoding="UTF-8") as file:
                     print(value, file=file)
 
+    # Copy over generic srdl2sv_interface_pkg
+    widget_if_rtl = pkg_resources.read_text(widgets, "srdl2sv_widget_if.sv")
+
+    out_if_file = f"{config['output_dir']}/srdl2sv_widget_if.sv"
+
+    with open(out_if_file, 'w', encoding="UTF-8") as file:
+        print(widget_if_rtl, file=file)
+
+    logger.info("Copied 'srdl2sv_widget_if.sv'")
+
     # Copy over widget RTL from widget directory
     try:
         widget_rtl = pkg_resources.read_text(widgets, f"srdl2sv_{config['bus']}.sv")
@@ -85,26 +102,6 @@ def main():
         # Bus might not have a corresponding SV file
         logger.info("Did not find a seperate SystemVerilog file for '%s' widget", config['bus'])
 
-    # Copy over generic srdl2sv_interface_pkg
-    if config['addrwidth_bus_spec']:
-        logger.info("Set address width to '%i', according to '%s' specification",
-                     config['addrwidth'], config['bus'])
-    else:
-        logger.info("Set address width to '%i'", config['addrwidth'])
-
-    widget_if_rtl = pkg_resources.read_text(widgets, 'srdl2sv_if_pkg.sv')
-
-    out_if_file = f"{config['output_dir']}/srdl2sv_if_pkg.sv"
-
-    with open(out_if_file, 'w', encoding="UTF-8") as file:
-        widget_if_rtl_parsed = widget_if_rtl.format(
-            regwidth_bit = addrmap.get_regwidth() - 1,
-            regwidth_byte = int(addrmap.get_regwidth() / 8) - 1,
-            addrwidth = config['addrwidth'] - 1)
-
-        print(widget_if_rtl_parsed,file=file)
-
-    logger.info("Copied 'srdl2sv_if_pkg.sv")
 
     # Print elapsed time
     logger.info("Elapsed time: %f seconds", time.time() - start)

tests/Makefile

@@ -37,9 +37,9 @@ default: $(ALL_COCOTB_TESTS)
 build_dirs/%/compile.f: systemrdl/%.rdl 
 	srdl2sv $? --out_dir $(shell dirname $@) --file_log_level DEBUG --stream_log_level DEBUG
 
-	ls $(PWD)/$(@D)/*_pkg.sv > $@
+	ls $(PWD)/$(@D)/*_if.sv > $@
 	ls $(PWD)/$(@D)/*amba*.sv >> $@
-	ls $(PWD)/$(@D)/*.sv | grep -v '.*_pkg.sv$$' | grep -v '.*amba.*' >> $@
+	ls $(PWD)/$(@D)/*.sv | grep -v '.*_if.sv$$' | grep -v '.*amba.*' >> $@
 
 
 clean: