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Replace old 'reg_clk' name by more generic 'clk'

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The reason is that the template will always assume that the
bus signals and the registers are synchronous. Designers should
implement possible synchronization logic outside of this block.
This commit is contained in:
Dennis Potter 2021-09-15 23:42:52 -07:00
parent 61cd1fbfe3
commit fea0019aa8
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 3 additions and 4 deletions
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3
srdl2sv/components/templates/addrmap.yaml
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@ -67,8 +67,7 @@ module_declaration:
<<UNINDENT>> <<UNINDENT>>
( (
<<INDENT>> <<INDENT>>
// Clock & Resets // Resets
input reg_clk,
{resets} {resets}
// Inputs // Inputs

4
srdl2sv/components/templates/fields.yaml
View File

@ -1,10 +1,10 @@
--- ---
sense_list_rst: sense_list_rst:
rtl: |- rtl: |-
always_ff @(posedge reg_clk or {rst_edge} {rst_name}) always_ff @(posedge clk or {rst_edge} {rst_name})
sense_list_no_rst: sense_list_no_rst:
rtl: |- rtl: |-
always_ff @(posedge reg_clk) always_ff @(posedge clk)
rst_field_assign: rst_field_assign:
rtl: |- rtl: |-
if ({rst_negl}{rst_name}) if ({rst_negl}{rst_name})