Commit Graph

10 Commits

Author SHA1 Message Date
6719d21423
Fix simple_rw_reg.rdl so that the test passes
The register was defined as a 64-bit register but the test was written
under the assumption it's a 32-bit register. Furthermore, the hardware
write-enable flag had to be set since all values would otherwise be
overwritten immediately.
2021-10-24 15:43:44 -07:00
49d1b598f0
Add setup.py to repository to install srdl2sv 2021-10-24 12:14:03 -07:00
4ba047dd2a
Extend test_simple_rw_reg with 3 more tests
The following tests are now included:

    - Check access to registers over AHB bus
    - Check access to register over HW interface
    - Check access to register over HW interface if hw_wr-input
      is disabled.
    - Check if the slave responds with a correct error sequence if
      an illegal address is accessed.
2021-10-11 23:49:31 -07:00
7d5ddaf47c
Add first simple test with a simple 2-dimensional array 2021-10-03 23:24:16 -07:00
aada5c5853
Prepare Makefiles for regression flow with CocoTB tests 2021-10-03 18:07:48 -07:00
d3bfdeb3f0
Buswidth is now variable, based on widest register
Fixes #2.
2021-09-26 21:16:49 -07:00
6359883c27
Finish initial version of interrupt suport, closes #1
The software is now able to create most interrupt combinations of
Section 9.9 of the SystemRDL 2.0 LRM. It supports
stickybit/non-stickybit interrupts, it support posedge, negedge,
bothedge, and level interrupts, and it is able to generate all
surrounding logic.

This commit also fixes a reset-bug that caused registers that were reset
to 0 to be not reset (because 'if not reset_value' will return True if
the 'reset_value' is 0).
2021-09-26 19:40:04 -07:00
8ea1ad97da
Fix AMBA AHB 3 Lite widget so that first register transactions succeed 2021-09-25 13:01:23 -07:00
61cd1fbfe3
Add directory that will contain SystemRDL files for tests 2021-09-13 22:09:04 -07:00
24d5534037
Add support for external registers
Every single field and every single alias (!) has its own
interface to the surrounding hardware. This is required
to give users the maximum amount of freedom when defining
certain properties in RDL.
2021-09-06 18:48:37 -07:00