Dennis/srdl2sv
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Dennis 44c87af8cb
Fix active_low/active_high reset bug 
A negation was added for active_high, rather than an active_low reset.
2021-05-24 11:49:51 +02:00
srdl2sv
Fix active_low/active_high reset bug
2021-05-24 11:49:51 +02:00
.gitignore
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
LIMITATIONS.md
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
Description
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asicfpgahardware-description-languagehdlrdlregister-description-languageregisterssystemrdlsystemrdl-compilersystemverilogverilog
713 KiB
Languages
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%