Dennis/srdl2sv
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Dennis 8d86010a0a Tweak default widths of I/O ports
2021-05-15 18:04:43 +02:00
srdl2sv
Tweak default widths of I/O ports
2021-05-15 18:04:43 +02:00
.gitignore
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
LIMITATIONS.md
Initial commit of SRDL2SV
2021-05-02 00:58:43 +02:00
Description
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asicfpgahardware-description-languagehdlrdlregister-description-languageregisterssystemrdlsystemrdl-compilersystemverilogverilog
GPL-3.0 713 KiB
Languages
Python 92.9%
SystemVerilog 5.7%
Makefile 1.4%