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Add support for rsvdset and rsvdsetX

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This commit is contained in:
Dennis Potter 2021-10-14 23:16:30 -07:00
parent 4ba047dd2a
commit 6e355c62af
Signed by: Dennis
GPG Key ID: 186A8AD440942BAF
2 changed files with 16 additions and 3 deletions
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8
srdl2sv/components/addrmap.py
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@ -32,6 +32,14 @@ class AddrMap(Component):
# Use global settings to define whether a component is already in a generate block # Use global settings to define whether a component is already in a generate block
glbl_settings['generate_active'] = False glbl_settings['generate_active'] = False
# Save whether 0, 1, or x must be set for reserved bits
if obj.get_property('rsvdset'):
glbl_settings['rsvd_val'] = "1"
elif obj.get_property('rsvdsetX'):
glbl_settings['rsvd_val'] = "x"
else:
glbl_settings['rsvd_val'] = "0"
# Empty dictionary of register objects # Empty dictionary of register objects
# We need a dictionary since it might be required to access the objects later # We need a dictionary since it might be required to access the objects later
# by name (for example, in case of aliases) # by name (for example, in case of aliases)

11
srdl2sv/components/register.py
View File

@ -157,7 +157,8 @@ class Register(Component):
current_bit = field.msb + 1 current_bit = field.msb + 1
if empty_bits > 0: if empty_bits > 0:
list_of_fields.append("{}'b0".format(empty_bits)) list_of_fields.append(
f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
list_of_fields.append("{}_q{}".format(field.path_underscored, self.genvars_str)) list_of_fields.append("{}_q{}".format(field.path_underscored, self.genvars_str))
@ -173,7 +174,8 @@ class Register(Component):
no_reads = not list_of_fields no_reads = not list_of_fields
if empty_bits > 0: if empty_bits > 0:
list_of_fields.append("{}'b0".format(empty_bits)) list_of_fields.append(
f"{{{empty_bits}{{1'b{self.glbl_settings['rsvd_val']}}}}}")
# Create list of mux-inputs to later be picked up by carrying addrmap # Create list of mux-inputs to later be picked up by carrying addrmap
self.sw_mux_assignment_var_name.append( self.sw_mux_assignment_var_name.append(
@ -482,12 +484,15 @@ class Register(Component):
self.obj.current_idx = [0] self.obj.current_idx = [0]
self.name = obj.inst_name self.name = obj.inst_name
# Save global settings
self.glbl_settings = glbl_settings
# Create mapping between (alias-) name and address # Create mapping between (alias-) name and address
self.name_addr_mappings = [ self.name_addr_mappings = [
(self.create_underscored_path_static(obj)[3], obj.absolute_address) (self.create_underscored_path_static(obj)[3], obj.absolute_address)
] ]
# Gnerate already started? # Geneate already started?
self.generate_active = glbl_settings['generate_active'] self.generate_active = glbl_settings['generate_active']
# Empty array for mux-input signals # Empty array for mux-input signals