Fundamental changes to the architecture of component classes
All components (e.g., fields, registers, addrmaps) are now children
of a common class Component. This common class has certain common
methods such as get_ports(), get_rtl(), or create_logger().
The AddrMap is now prepared to support alias registers by saving the
registers in a dictionary. That way, registers can easily be accessed
once an alias to a register is found. Furthermore, the addrmap template
is now also loaded from a YAML file. Lastly, the first preparements to
insert ports into the addrmap module are made.
For templates, the indents do not need to be added anymore to the
template. Now, a seperate method will automatically indent the RTL
based on simple rules (e.g., increment indent if `begin` is found).
The CLI also supports settings for the tabs (i.e., real tabs or spaces
and the tab width).
A lot of functionality from the __init__() method of the field class
got reorganized. More logic will be reorganized in the future.
2021-05-14 22:29:59 +00:00
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---
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2021-06-26 09:37:56 +00:00
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header: |-
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/*****************************************************************
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*
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* ███████╗██████╗ ██████╗ ██╗ ██████╗ ███████╗██╗ ██╗
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* ██╔════╝██╔══██╗██╔══██╗██║ ╚════██╗██╔════╝██║ ██║
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* ███████╗██████╔╝██║ ██║██║ █████╔╝███████╗██║ ██║
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* ╚════██║██╔══██╗██║ ██║██║ ██╔═══╝ ╚════██║╚██╗ ██╔╝
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* ███████║██║ ██║██████╔╝███████╗███████╗███████║ ╚████╔╝
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* ╚══════╝╚═╝ ╚═╝╚═════╝ ╚══════╝╚══════╝╚══════╝ ╚═══╝
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*
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* The present RTL was generated by srdl2sv v{version}. The RTL and all
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* templates the RTL is derived from are licensed under the MIT
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* license. The license is shown below.
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*
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* srdl2sv itself is licensed under GPLv3.
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*
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* Maintainer : Dennis Potter <dennis@dennispotter.eu>
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2021-10-31 02:37:02 +00:00
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* Report Bugs: https://github.com/Silicon1602/srdl2sv/issues
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2021-06-26 09:37:56 +00:00
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*
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* ===GENERATION INFORMATION======================================
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*
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* Generation information:
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* - User: : {user}
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* - Time : {time}
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* - Path : {path}
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* - RDL file : {rdl_file}
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* - Hostname : {host}
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*
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* RDL include directories:
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* - {incdirs}
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*
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* Commandline arguments to srdl2sv:
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* - {config}
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*
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* ===LICENSE OF {addrmap}.SV=====================================
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*
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2021-08-15 21:12:21 +00:00
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* Copyright {year} Dennis Potter <dennis@dennispotter.eu>
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2021-06-26 09:37:56 +00:00
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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****************************************************************/
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2021-11-06 17:57:46 +00:00
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description:
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2021-10-17 07:53:22 +00:00
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rtl: |-
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/*******************************************************************
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/**ADDRMAP DESCRIPTION**********************************************
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/*******************************************************************
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{desc}
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/*******************************************************************/
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2021-06-26 09:37:56 +00:00
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2021-06-03 10:02:27 +00:00
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module_declaration:
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rtl: |-
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module {name}
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2021-06-25 09:33:57 +00:00
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<<INDENT>>
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2021-06-03 14:46:49 +00:00
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{import_package_list}
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2021-06-25 09:33:57 +00:00
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<<UNINDENT>>
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2021-06-03 10:02:27 +00:00
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(
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2021-06-25 09:33:57 +00:00
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<<INDENT>>
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2021-11-27 00:15:00 +00:00
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// Reset signals declared for registers
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2021-06-03 10:02:27 +00:00
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{resets}
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2021-05-24 12:42:24 +00:00
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2021-11-27 00:15:00 +00:00
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{ports}
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Fundamental changes to the architecture of component classes
All components (e.g., fields, registers, addrmaps) are now children
of a common class Component. This common class has certain common
methods such as get_ports(), get_rtl(), or create_logger().
The AddrMap is now prepared to support alias registers by saving the
registers in a dictionary. That way, registers can easily be accessed
once an alias to a register is found. Furthermore, the addrmap template
is now also loaded from a YAML file. Lastly, the first preparements to
insert ports into the addrmap module are made.
For templates, the indents do not need to be added anymore to the
template. Now, a seperate method will automatically indent the RTL
based on simple rules (e.g., increment indent if `begin` is found).
The CLI also supports settings for the tabs (i.e., real tabs or spaces
and the tab width).
A lot of functionality from the __init__() method of the field class
got reorganized. More logic will be reorganized in the future.
2021-05-14 22:29:59 +00:00
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2021-06-25 09:33:57 +00:00
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<<UNINDENT>>
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2021-06-03 10:02:27 +00:00
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);
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import_package:
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rtl: |-
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2021-06-23 23:00:36 +00:00
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import {name}_pkg::*;
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2021-06-03 10:02:27 +00:00
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reset_port:
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rtl:
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2021-11-27 00:52:46 +00:00
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input {name},
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2021-11-27 00:15:00 +00:00
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port:
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rtl: |-
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{direction:6} {signal_type:{signal_width}} {name:{name_width}}{unpacked_dim},
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2021-06-05 13:37:09 +00:00
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signal_declaration: |-
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{type:{signal_width}} {name:{name_width}}{unpacked_dim};
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2021-06-03 10:02:27 +00:00
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package_declaration:
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rtl: |-
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package {name}_pkg;
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{pkg_content}
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endpackage
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enum_declaration:
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rtl: |-
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typedef enum logic [{width}:0] {{
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{enum_var_list}
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}} {name};
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enum_var_list_item:
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rtl: |-
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{name:{max_name_width}} = {width}'d{value}
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2021-06-22 23:03:11 +00:00
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read_mux:
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rtl: |-
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// Read multiplexer
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always_comb
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begin
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2021-10-20 06:33:59 +00:00
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unique case (1'b1)
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2021-06-22 23:03:11 +00:00
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{list_of_cases}
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endcase
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end
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2021-06-24 23:35:55 +00:00
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default_mux_case:
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rtl: |-
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2021-09-06 07:26:08 +00:00
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default:
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begin
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2021-09-07 01:48:37 +00:00
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// If the address is not found, return an error
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2021-10-28 06:27:29 +00:00
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widget_if.r_data = 0;
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widget_if.err = 1;
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widget_if.rdy = widget_if.r_vld || widget_if.w_vld;
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2021-09-06 07:26:08 +00:00
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end
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2021-06-22 23:03:11 +00:00
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list_of_mux_cases:
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rtl: |-
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2021-10-20 06:58:02 +00:00
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{active_wire}:
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2021-09-06 07:26:08 +00:00
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begin
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2021-10-28 06:27:29 +00:00
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widget_if.r_data = {widget_if_r_data};
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widget_if.err = {widget_if_err};
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widget_if.rdy = {widget_if_rdy};
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2021-09-06 07:26:08 +00:00
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end
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