Every time an addrmap is detected within another addrmap, a new context
will be opened and a separate RTL file will be created.
All addrmaps will have the same bus-wdiget, but it might be possible
that different addrmaps have different maximum regwidths. For that
reason, it was necessary to change the non-generic srd2sv_if_pkg to a
parametrizable interface.
Almost all changes to the templates in this commit are due to name
changes from 'b2r' and 'r2b' to 'widget_if'.
The reason is that the template will always assume that the
bus signals and the registers are synchronous. Designers should
implement possible synchronization logic outside of this block.
Every single field and every single alias (!) has its own
interface to the surrounding hardware. This is required
to give users the maximum amount of freedom when defining
certain properties in RDL.
The error indication is generated if:
- A non-existent register gets read
- An existent register gets read but not a single bit can be
succesfully read or written. As soon as 1 bit succeeds don't
return an error.
This allows a designer to add markers to the template to indicate where
a new level of indentation should start or end. This is apart fromt he
auto-indents caused by "case", "begin", or "{".
Evaluating every single wire is maybe not the best way to do this, but
it is probably better than writing a very exotic SV construct with
(for-)loops, breaks, and a lot of conditions. Most synthesis tools are
pretty good at recognizing this case-construct and generating a good
mutliplexer.
This adds initial support for a dynamic bus-protocol to internal
register logic SHIM. The chosen default protocol at this point is AMBA 3
AHB Lite and the logic is still empty.
-> TODO: Adding the widget instantiation showed that it is required
to have a better interface to parametrize ports & signals in the
YAML. At this point, only a limited set of variables are supported.
Furthermore, all remaining Verilator compilation issues in the field are
resolved. Those were mostly related to non-declared wires and wrongly named
wires.
This commit only adds package supports for addrmaps. It should be
relatively easy to extend this for regfiles in a future commit.
Furthermore, this commit adds support to _disable_ enums.
These two special kind of resets are now recognized by the compiler and
are propagated to all regfiles, registers, and fields.
Furthermore, every object has a set of resets which will be used to
generate a seperate input section for resets in the addrmap.
Fields that are encoded as enumerations are now recognized by the
application. All relevant information will be saved in the Field Object
and the variables and I/O list will be generated accordingly.
This commit also adds dynamic padding of the I/O and variable lists.
Still lacking is the automatic generation of SV packages.
Now, every snippet of RTL in the YAML file can also hold internal
variables (i.e., signals), input or output ports. Furthermore, the
input/output port lists are replaced by a dictionary to prevent
duplicate entries.
All components (e.g., fields, registers, addrmaps) are now children
of a common class Component. This common class has certain common
methods such as get_ports(), get_rtl(), or create_logger().
The AddrMap is now prepared to support alias registers by saving the
registers in a dictionary. That way, registers can easily be accessed
once an alias to a register is found. Furthermore, the addrmap template
is now also loaded from a YAML file. Lastly, the first preparements to
insert ports into the addrmap module are made.
For templates, the indents do not need to be added anymore to the
template. Now, a seperate method will automatically indent the RTL
based on simple rules (e.g., increment indent if `begin` is found).
The CLI also supports settings for the tabs (i.e., real tabs or spaces
and the tab width).
A lot of functionality from the __init__() method of the field class
got reorganized. More logic will be reorganized in the future.
Dennis Potter