The former issue was a Lint warning. HADDR % HSIZE is a modulo operation
of a 32-bit and 3-bit variable. It is cleaner to only use the LSB of
HADDR.
Furthermore, Verilator does not support unpacked arrays in packages.
Every single field and every single alias (!) has its own
interface to the surrounding hardware. This is required
to give users the maximum amount of freedom when defining
certain properties in RDL.
The error indication is generated if:
- A non-existent register gets read
- An existent register gets read but not a single bit can be
succesfully read or written. As soon as 1 bit succeeds don't
return an error.
The main difference in this release
(https://github.com/SystemRDL/systemrdl-compiler/releases/tag/v1.19.0)
is that FieldNode.get_property('resetsignal') will now default to
finding the nearest in-scope field reset signal if not explicitly set.
The same is true for the cpuif-signal.
Before this commit, the addmap-class searched for resetsignal and cpuif
signals and saved it for the fields to be picked up later. This code is
now not required anymore
The counter now covers more corner cases regarding saturation.
Furthermore, a bug that caused incr & decr-counters to always
inadvertently increment and decrement, even if only one of the two
signals was set.
Furthermore, the overflow signal is now generated in RTL.
Still missing:
- incrthreshold/decrthreshold is not yet supported
- It is not yet supported to assign an underflow/overflow to the
input of another counter.
For addrmaps, the addrmaps appeared twice. It was better anyway to use a
variable name that gets build in create_underscored_path(). This method
was not yet present when the logger was first instantiated.
The software itself is licensed under the copy-left GPL-3.0 license. All
RTL (i.e., templates and widgets) are licensed under the MIT license.
Therefore, the generated RTL will not be subject to the GPL-3.0 but to
the MIT license.
This allows a designer to add markers to the template to indicate where
a new level of indentation should start or end. This is apart fromt he
auto-indents caused by "case", "begin", or "{".
This ensures that code is compilation clean again. Prior to this change,
the multiplexer was reading from variables that were declared inside of
generate-scopes.
Furthermore, a small bug regarding the dimension detection of registers
was fixed. If a register wasn't multidimensional itself, but its parent
is, the multidimensionalness wasn't detected.
Evaluating every single wire is maybe not the best way to do this, but
it is probably better than writing a very exotic SV construct with
(for-)loops, breaks, and a lot of conditions. Most synthesis tools are
pretty good at recognizing this case-construct and generating a good
mutliplexer.
This required some fundamental changes. One of them is that YAML fields
are now processed in a more systematic way in which all fields are
passed via a dictionary. That way, some of the fields are not bound to
the original object anymore.
This adds initial support for a dynamic bus-protocol to internal
register logic SHIM. The chosen default protocol at this point is AMBA 3
AHB Lite and the logic is still empty.
-> TODO: Adding the widget instantiation showed that it is required
to have a better interface to parametrize ports & signals in the
YAML. At this point, only a limited set of variables are supported.
Furthermore, all remaining Verilator compilation issues in the field are
resolved. Those were mostly related to non-declared wires and wrongly named
wires.
This is caused by register access properties that don't have a
condition. As soon as such a property is encountered, no more branches
shall be added to that register.
