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Author	SHA1	Message	Date
Dennis	9cb53f0fb0	Add simple_rw_reg example with reset signals	2021-11-26 16:53:06 -08:00
Dennis	d8add0d5f2	Add more padding between 'input' and name of reset-signal	2021-11-26 16:52:46 -08:00
Dennis	07855015b0	Remove log file, used while debugging with Verilator	2021-11-26 16:43:54 -08:00
Dennis	2f76e31c12	Update examples with changes from ae83dceb	2021-11-26 16:33:41 -08:00
Dennis	ae83dceb7a	Closes #13: I/O ports are now grouped and are tied to the register the belong to	2021-11-26 16:32:36 -08:00
Dennis	9d05c90d50	Add hwclr property to counters example	2021-11-17 22:21:43 -08:00
Dennis	4cb00dc38f	Add information on HTML/UVM/IP-XACT tools and add more limitations	2021-11-07 12:00:47 -08:00
Dennis	8fd5a202e8	Add examples build to regression Makefile	2021-11-07 11:53:34 -08:00
Dennis	719b013b88	Fix Python lint warnings related to logging	2021-11-07 11:44:07 -08:00
Dennis	73dfed0146	Regenerate aliases example with fix from 33b6e2e	2021-11-07 11:38:39 -08:00
Dennis	33b6e2e946	Fix regression in OnRead and OnWrite properties ... The following tests were failing: - test_swacc_properties.test_rclr_rset - test_swacc_properties.test_rclr_rset_hw_precedence The reason for this failure was incorrect usage of the assignment expression. Due to the lack of parentheses, the onread/onwrite variable would mostly evaluate to False.	2021-11-07 11:36:05 -08:00
Dennis	0dba725fd3	Add external alias in regfile example to aliases-example	2021-11-07 11:19:44 -08:00
Dennis	3e7344a79c	Fix wrong scope names and compilation issues with external aliases	2021-11-07 11:19:03 -08:00
Dennis	1b4c071a85	Add Verilator obj_dir directory to .gitignore	2021-11-06 22:50:58 -07:00
Dennis	f81cae107d	Add example with aliases	2021-11-06 22:47:47 -07:00
Dennis	0887372dbd	Fix alias bugs introduced when adding external registers ... Furthermore, some compilation bugs were added when optimizing away swacc and swmod wires when not required.	2021-11-06 22:45:34 -07:00
Dennis	c589a17ea5	Add counter-example	2021-11-06 18:28:21 -07:00
Dennis	17c1b9b9a0	Fix bug with static values for saturate/threshold values	2021-11-06 18:24:42 -07:00
Dennis	b44813e0c5	Fix addrmap & memory/regfile/register/field-naming collision ... For almost all variables, the addrmap is stripped of the name. However, when a memory/regfile/register/field had the same name as the addrmap, a part of that name would also be stripped.	2021-11-06 18:00:17 -07:00
Dennis	8fbf800c4f	Fix bug with dynamic saturate values and fix Lint warnings ... Two categories Lint warnings occured: - Width mismatches, since integers are 32-bit wide according to the SV LRM. - Constant saturate values, because values could get larger than 32-bit and smaller than 0.	2021-11-06 17:36:45 -07:00
Dennis	5d3fd14144	Fix bug that prevented descriptions from being generated inserted	2021-11-06 10:57:46 -07:00
Dennis	85598af11e	Closes #11: Add flag to turn off error-response on illegal addresses	2021-11-06 10:25:32 -07:00
Dennis	fc26817c33	Update Makefiles in examples directory to also invoke a Verilator compile	2021-11-04 23:38:50 -07:00
Dennis	ba45cfc64a	Add parameters example RDL file	2021-11-04 23:33:06 -07:00
Dennis	cc0d961a41	Regenerate examples with changes from 95b9a5a4 and 85dc719	2021-11-02 23:28:58 -07:00
Dennis	85dc71919e	Fix bug introduced in 95b9a5a4 that broke registers with just 1 byte	2021-11-02 23:28:37 -07:00
Dennis	9be761b53d	Update example's Makefile to always rebuild if srdl2sv updates	2021-11-02 23:20:35 -07:00
Dennis	95b9a5a46a	Gather bit-ranges of byte-enable signal in error-wire ... Previously, the error wire would be assigned like this: assign example_reg_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); Now, this same line is simplified to: assign example_reg_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0])));	2021-11-02 23:17:28 -07:00
Dennis	8df25ece01	Closes #10: sw read/write side-effects now honor byte-enables if enabled	2021-10-31 22:36:51 -07:00
Dennis	22a822c097	Add initial version of sofware access property tests ... At this point, only the read-side-effect tests are implemented.	2021-10-31 21:56:08 -07:00
Dennis	d4d5868382	Update Makefile to rebuild on srdl2sv changes and better error reporting	2021-10-31 21:54:11 -07:00
Dennis	f0f2ef3d78	Add module description to test_simple_rw_reg.py	2021-10-31 19:43:14 -07:00
Dennis	247f1a7575	Update CLI arguments in README description	2021-10-31 19:35:36 -07:00
Dennis	6c9df1cc02	Add Makefiles in example/ to easily rebuild all examples	2021-10-31 16:38:27 -07:00
Dennis	82b2490256	Update examples with changes from a43cd2e (issue #7)	2021-10-31 16:01:44 -07:00
Dennis	a43cd2ea6c	Closes #7: Add flag that disables unpacked arrays	2021-10-31 15:58:31 -07:00
Dennis	a871e9a906	Add example to show handling of SystemRDL enums	2021-10-31 13:59:51 -07:00
Dennis	0371bef439	Long CLI arguments now use dashes rather than underscores	2021-10-31 13:53:11 -07:00
Dennis	ed167c05de	Update AMBA 3 AHB Lite widget in examples with 33c92c8 (issue #9)	2021-10-30 23:35:38 -07:00
Dennis	33c92c8994	Closes #9: Error returns from regblock now actually get processed by AHB widget	2021-10-30 23:30:55 -07:00
Dennis	031e413d17	Fix test_simple_rw_reg.test_illegal_address so that it always recognizes issue #9 ... Before this fix, the bug would only pop up for addresses that were dividable by 4. Otherwise, the AMBA AHB 3 Lite widget would return an error response because of an illegal HSIZE/HADDR combination.	2021-10-30 23:27:14 -07:00
Dennis	7efe7c4cea	Update examples with changes from e46e51f and a148e8b ... The former commit implements fixes that were required for issue #8. The latter only updated the link to report bugs.	2021-10-30 19:38:43 -07:00
Dennis	a148e8bbd1	Update link in header to report bugs	2021-10-30 19:37:02 -07:00
Dennis	e46e51f3cf	Closes #8: Certain fields shall be implemented as wires or constants ... The software now detects whether a field shall be implemented with flops, with wires, or as a constant. Everything should now follow Table 12 and Section 9.5.1 of the SystemRDL 2.0 LRM.	2021-10-30 19:33:14 -07:00
Dennis	5a00d48c34	Add RDL example with compiled hierarchical regfiles	2021-10-28 22:55:28 -07:00
Dennis	738be4ddc4	Update README.md with output-file information	2021-10-27 23:57:15 -07:00
Dennis	e6cfec9c32	Update srdl2sv examples with widget<->interface changes ... These changes were introduced in 85f7808 in order to close #4.	2021-10-27 23:33:42 -07:00
Dennis	85f7808362	Closes #4: Add support for hierarchical addrmaps ... Every time an addrmap is detected within another addrmap, a new context will be opened and a separate RTL file will be created. All addrmaps will have the same bus-wdiget, but it might be possible that different addrmaps have different maximum regwidths. For that reason, it was necessary to change the non-generic srd2sv_if_pkg to a parametrizable interface. Almost all changes to the templates in this commit are due to name changes from 'b2r' and 'r2b' to 'widget_if'.	2021-10-27 23:27:29 -07:00
Dennis	ac693f0c02	Change default logging settings ... STDOUT now will get INFO-level logging by default. The file output will get no logging by default.	2021-10-27 23:22:27 -07:00
Dennis	b8e9adb1f0	Add hierarchical interrupts under examples ... The SystemRDL that was added comes from Section 17.2 "Understanding hierarchical interrupts in SystemRDL" of the SystemRDL 2.0 LRM. The present code succesfully compiles.	2021-10-24 23:33:01 -07:00