Apart from adding regfiles in general (which is mostly a combination of
addrmap and register code), the stride/array_dimension code had to be
revisted to be correct for multi dimensional arrays with multi
dimensional registers.
Lastly, the logger instantiation has been moved to the __init__()
method of `Component`.
These two special kind of resets are now recognized by the compiler and
are propagated to all regfiles, registers, and fields.
Furthermore, every object has a set of resets which will be used to
generate a seperate input section for resets in the addrmap.
Fields that are encoded as enumerations are now recognized by the
application. All relevant information will be saved in the Field Object
and the variables and I/O list will be generated accordingly.
This commit also adds dynamic padding of the I/O and variable lists.
Still lacking is the automatic generation of SV packages.
Now, every snippet of RTL in the YAML file can also hold internal
variables (i.e., signals), input or output ports. Furthermore, the
input/output port lists are replaced by a dictionary to prevent
duplicate entries.
This commit also created a seperate private method for access related
RTL and for the always_ff header.
Furthermore, a bug which caused the singlepulse property to always show
up was resolved.
Lastly, the summary method was made truely public. So, rather than
writing to the RTL list, it now returns a list and the calling
method/function can decide what to do with that list.
In case a register isn't instantiated as an array, the stride
value the compiler returns is set to 'None'. The RTL generator
should translate it to '0' (since it doesn't matter anyway).
All components (e.g., fields, registers, addrmaps) are now children
of a common class Component. This common class has certain common
methods such as get_ports(), get_rtl(), or create_logger().
The AddrMap is now prepared to support alias registers by saving the
registers in a dictionary. That way, registers can easily be accessed
once an alias to a register is found. Furthermore, the addrmap template
is now also loaded from a YAML file. Lastly, the first preparements to
insert ports into the addrmap module are made.
For templates, the indents do not need to be added anymore to the
template. Now, a seperate method will automatically indent the RTL
based on simple rules (e.g., increment indent if `begin` is found).
The CLI also supports settings for the tabs (i.e., real tabs or spaces
and the tab width).
A lot of functionality from the __init__() method of the field class
got reorganized. More logic will be reorganized in the future.
Previously, the SystemVerilog was simply written to the shell. This
started to become too long to be readable. Now, the application dumps
everything to the output directory that is defined on the command line
(or the default).
Temporary workaround: the AddrMap component's RTL is completely
overwritten by the Register's RTL. This is temporary until the AddrMap
also uses a YAML file.
This mechanism has custom coloring, support to dump in file and
on the commandline and support to turn either or both off. cli/cli.py
provies a function that can be called in each module to instantiate
a logger for that module.
This wrapper lives in a seperate module and class so that possible
processing of arguments can be done before the config dictionary
gets passed to the compiler.
By using a dictionary, it will be easier to mix & match the RTL
order dependend on the properties of the field.
This commit also adds anded/ored/xored properties.
The compiler in this commit is still useless and only contains a
very rough skeleton of the code. SRDL2SV is only able to
create a simple register with hw=rw/sw=rw fields.
Dennis Potter