This happened in AddrMap and RegFile because a the width of a new
variable 'new_child' is performed. However, SignalNodes will not create
such a child.
If this option is defined, there will be a direct interface to the b2r
and r2b interface. The structs will be flattened out to wires for legacy
reasons.
This closes#3.
The register was defined as a 64-bit register but the test was written
under the assumption it's a 32-bit register. Furthermore, the hardware
write-enable flag had to be set since all values would otherwise be
overwritten immediately.
For example, most methods relating to dimensions or genvars were moved
to the Components class.
Furthermore, some more care was taken of _ or __ prefixes for methods:
- No method-prefix: Public variable that is will be called by
non-related functions and methods.
- _ method-prefix: Method will be called by class or class that
inerhits class
- __ method-prefix: Method will be called by class itself only
The following tests are now included:
- Check access to registers over AHB bus
- Check access to register over HW interface
- Check access to register over HW interface if hw_wr-input
is disabled.
- Check if the slave responds with a correct error sequence if
an illegal address is accessed.
In dc37c879, some properties got saved in self.properties of a
Component. In that commit, self.properties['sw_rd'] never got set.
For that reason, external registers with a read-interface were broken.
When a regfile did use enumerations from multiple scopes this messed up
the eventual packages because every regfile only assumed 1 scope. This
is fixed now.
TODO: Check what happens if enums are defined in the register scope.
The software is now able to create most interrupt combinations of
Section 9.9 of the SystemRDL 2.0 LRM. It supports
stickybit/non-stickybit interrupts, it support posedge, negedge,
bothedge, and level interrupts, and it is able to generate all
surrounding logic.
This commit also fixes a reset-bug that caused registers that were reset
to 0 to be not reset (because 'if not reset_value' will return True if
the 'reset_value' is 0).
Up to this point, interrupt outputs are generated and intr, enable,
mask, haltenable, and haltmask are supported. stick, stikcybit and the
different types of interrupts are not yet supported.
This commit also removes the option to turn off santiy checking. This is
a bad idea anyway...
The reason is that the template will always assume that the
bus signals and the registers are synchronous. Designers should
implement possible synchronization logic outside of this block.
The former issue was a Lint warning. HADDR % HSIZE is a modulo operation
of a 32-bit and 3-bit variable. It is cleaner to only use the LSB of
HADDR.
Furthermore, Verilator does not support unpacked arrays in packages.
Dennis Potter