Commit Graph

76 Commits

Author SHA1 Message Date
fea0019aa8
Replace old 'reg_clk' name by more generic 'clk'
The reason is that the template will always assume that the
bus signals and the registers are synchronous. Designers should
implement possible synchronization logic outside of this block.
2021-09-15 23:42:52 -07:00
61cd1fbfe3
Add directory that will contain SystemRDL files for tests 2021-09-13 22:09:04 -07:00
85aa2f903c
Flops must not update when HREADYOUT == 0, not when r2b.rdy == 0 2021-09-13 21:52:35 -07:00
a27b57009b
Fix two issues to get AMBA widget compile clean under Verilator
The former issue was a Lint warning. HADDR % HSIZE is a modulo operation
of a 32-bit and 3-bit variable. It is cleaner to only use the LSB of
HADDR.

Furthermore, Verilator does not support unpacked arrays in packages.
2021-09-12 19:44:42 -07:00
240fba8e12
Resolve bug for addrmaps without any genvars
In this case, there would be a line with `genvars ;`. This is not
compilable by SystemVerilog compilers.
2021-09-12 19:44:42 -07:00
17f1877390
Add very basic, incomplete statemachine for AHB protocol 2021-09-12 17:13:44 -07:00
6142a13653
Add genvar-key to write-signals of external registers 2021-09-12 17:09:33 -07:00
b89bf3663f
Fix issue with read-mux assignment for multidimensional registers 2021-09-12 16:44:37 -07:00
5475bbf62d
Fix issue that causes 'input None' if no reset is present for a field 2021-09-06 22:42:32 -07:00
24d5534037
Add support for external registers
Every single field and every single alias (!) has its own
interface to the surrounding hardware. This is required
to give users the maximum amount of freedom when defining
certain properties in RDL.
2021-09-06 18:48:37 -07:00
a3b6e1caf8
Add file-exist check for input file 2021-09-06 11:58:01 -07:00
4f2ac8868a
Rename regs.yaml to register.yaml for consistency reasons 2021-09-06 00:29:29 -07:00
c689190080
Add proper support for rdy & error indication in read multiplexer
The error indication is generated if:
    - A non-existent register gets read
    - An existent register gets read but not a single bit can be
      succesfully read or written. As soon as 1 bit succeeds don't
      return an error.
2021-09-06 00:26:08 -07:00
2f38d30d76
Fix assignment to _rd_mux_in for arrays 2021-08-22 21:50:58 -07:00
08b7de9544
Fix read-multiplexer bug in case a reg is _not_ an array 2021-08-22 21:43:53 -07:00
d298e79ec1
Fix bug where an empty search path caused srdl2sv to crash 2021-08-22 21:27:44 -07:00
8881821252
Give more consistent names to modules and packages 2021-08-22 20:46:35 -07:00
5e4a954a0c
Add _very incomplete_ AMBA 3 AHB Lite widget
This is just a start on the first widget. It is still very limited and
not yet functional in any way.
2021-08-22 20:38:56 -07:00
145ac70123
Add email address to MIT license 2021-08-15 14:12:21 -07:00
78742daba7
Add support for 'next' property to fields 2021-08-15 14:10:22 -07:00
a74377bae7
Add underflow property and checker if referenced properties exist 2021-08-15 12:56:41 -07:00
1d5bc8b75e
Fix assignment of overflow to increment input of counter 2021-08-15 12:28:07 -07:00
fd75e4c84c
Update systemrdl-compiler to v1.19.0
The main difference in this release
(https://github.com/SystemRDL/systemrdl-compiler/releases/tag/v1.19.0)
is that FieldNode.get_property('resetsignal') will now default to
finding the nearest in-scope field reset signal if not explicitly set.
The same is true for the cpuif-signal.

Before this commit, the addmap-class searched for resetsignal and cpuif
signals and saved it for the fields to be picked up later. This code is
now not required anymore
2021-08-15 11:46:40 -07:00
1d50b2b457
Add incrthreshold/decrthreshold support
It is still not possible to assign overflow/threshold signals to any
input of a different register!
2021-06-29 00:14:51 +02:00
18204d9a3e
Improve counter property
The counter now covers more corner cases regarding saturation.
Furthermore, a bug that caused incr & decr-counters to always
inadvertently increment and decrement, even if only one of the two
signals was set.

Furthermore, the overflow signal is now generated in RTL.

Still missing:
    - incrthreshold/decrthreshold is not yet supported
    - It is not yet supported to assign an underflow/overflow to the
      input of another counter.
2021-06-28 23:58:45 +02:00
4144329f3f
Add comment to delineate between counters and multiplexer assignment 2021-06-28 23:57:32 +02:00
a0dd59d19a
Add hwenable and hwmask property 2021-06-28 12:48:17 +02:00
c00550a166
Add hwset & hwclr properties 2021-06-28 00:37:54 +02:00
9385f59ac7
Add counters (w/o threshold property and w/o an overflow property)
Saturating and non-saturating counters are supported. Furthermore,
dynamic and static incrvalues and the incrwidth property is supported.
2021-06-27 17:04:48 +02:00
f50d65d2d2
Fix path in logger object
For addrmaps, the addrmaps appeared twice. It was better anyway to use a
variable name that gets build in create_underscored_path(). This method
was not yet present when the logger was first instantiated.
2021-06-27 11:09:10 +02:00
5ed7cccd7f
Cleanup __add_swmod_swacc and extend verbosity of warnings/debug 2021-06-27 00:21:41 +02:00
2e22d82146
Add swmod and swacc properties and fix field-range bug 2021-06-27 00:09:28 +02:00
95fef548cf
Add header with license and generation information to addrmap 2021-06-26 11:37:56 +02:00
6deb772196
Add LICENSEs to srdl2sv
The software itself is licensed under the copy-left GPL-3.0 license. All
RTL (i.e., templates and widgets) are licensed under the MIT license.
Therefore, the generated RTL will not be subject to the GPL-3.0 but to
the MIT license.
2021-06-26 11:08:13 +02:00
baf08d2343
Add bus_clk/bus_rst_n ports to widget (rather than (only) reg_clk) 2021-06-25 11:50:06 +02:00
6565c33445
Resolve Python Lint warnings (e.g., unnecessary list comprehensions) 2021-06-25 11:46:18 +02:00
c7f571b909
Fix missing multiplexer entries for single-dimension registers 2021-06-25 11:45:47 +02:00
695de2d330
Add <<INDENT>> and <<UNINDENT>> helpers to template
This allows a designer to add markers to the template to indicate where
a new level of indentation should start or end. This is apart fromt he
auto-indents caused by "case", "begin", or "{".
2021-06-25 11:33:57 +02:00
01a696c2b3
Add default value to mux to prevent an inferred latch 2021-06-25 01:35:55 +02:00
ce4782c11d
Pull declaration of variables outside of generate scope
This ensures that code is compilation clean again. Prior to this change,
the multiplexer was reading from variables that were declared inside of
generate-scopes.

Furthermore, a small bug regarding the dimension detection of registers
was fixed. If a register wasn't multidimensional itself, but its parent
is, the multidimensionalness wasn't detected.
2021-06-25 01:20:32 +02:00
3089edc20d
Add indentation to case-block 2021-06-24 01:05:55 +02:00
31179eeecc
Add get_package_rtl()-method to regfiles 2021-06-24 01:00:36 +02:00
0db14e8815
Add missing sw_rd_bus-input port to widget 2021-06-24 00:58:42 +02:00
32c6fc3c4a
Add read-multiplexer logic
Evaluating every single wire is maybe not the best way to do this, but
it is probably better than writing a very exotic SV construct with
(for-)loops, breaks, and a lot of conditions. Most synthesis tools are
pretty good at recognizing this case-construct and generating a good
mutliplexer.
2021-06-23 01:03:11 +02:00
b2c756af41
Add support for alias registers
This required some fundamental changes. One of them is that YAML fields
are now processed in a more systematic way in which all fields are
passed via a dictionary. That way, some of the fields are not bound to
the original object anymore.
2021-06-12 01:28:29 +02:00
9deb28ce4e
Add initial version of widget-code and fix remaining SV compiler errors
This adds initial support for a dynamic bus-protocol to internal
register logic SHIM. The chosen default protocol at this point is AMBA 3
AHB Lite and the logic is still empty.

    -> TODO: Adding the widget instantiation showed that it is required
    to have a better interface to parametrize ports & signals in the
    YAML. At this point, only a limited set of variables are supported.

Furthermore, all remaining Verilator compilation issues in the field are
resolved. Those were mostly related to non-declared wires and wrongly named
wires.
2021-06-05 15:37:09 +02:00
21abdefac0
Add genvar declaration to addrmap 2021-06-03 18:07:17 +02:00
f4432f5b49
Add check for uniqueness of enum member names within a scope 2021-06-03 16:46:49 +02:00
ec492d619a
Fix widths in OnWrite and OnRead properties 2021-06-03 16:11:58 +02:00
ee20126da6
Add missing 'endmodule' keyword to addrmap 2021-06-03 12:56:26 +02:00