For example, most methods relating to dimensions or genvars were moved
to the Components class.
Furthermore, some more care was taken of _ or __ prefixes for methods:
- No method-prefix: Public variable that is will be called by
non-related functions and methods.
- _ method-prefix: Method will be called by class or class that
inerhits class
- __ method-prefix: Method will be called by class itself only
In dc37c879, some properties got saved in self.properties of a
Component. In that commit, self.properties['sw_rd'] never got set.
For that reason, external registers with a read-interface were broken.
The software is now able to create most interrupt combinations of
Section 9.9 of the SystemRDL 2.0 LRM. It supports
stickybit/non-stickybit interrupts, it support posedge, negedge,
bothedge, and level interrupts, and it is able to generate all
surrounding logic.
This commit also fixes a reset-bug that caused registers that were reset
to 0 to be not reset (because 'if not reset_value' will return True if
the 'reset_value' is 0).
Up to this point, interrupt outputs are generated and intr, enable,
mask, haltenable, and haltmask are supported. stick, stikcybit and the
different types of interrupts are not yet supported.
This commit also removes the option to turn off santiy checking. This is
a bad idea anyway...
Every single field and every single alias (!) has its own
interface to the surrounding hardware. This is required
to give users the maximum amount of freedom when defining
certain properties in RDL.
The error indication is generated if:
- A non-existent register gets read
- An existent register gets read but not a single bit can be
succesfully read or written. As soon as 1 bit succeeds don't
return an error.
The main difference in this release
(https://github.com/SystemRDL/systemrdl-compiler/releases/tag/v1.19.0)
is that FieldNode.get_property('resetsignal') will now default to
finding the nearest in-scope field reset signal if not explicitly set.
The same is true for the cpuif-signal.
Before this commit, the addmap-class searched for resetsignal and cpuif
signals and saved it for the fields to be picked up later. This code is
now not required anymore
The counter now covers more corner cases regarding saturation.
Furthermore, a bug that caused incr & decr-counters to always
inadvertently increment and decrement, even if only one of the two
signals was set.
Furthermore, the overflow signal is now generated in RTL.
Still missing:
- incrthreshold/decrthreshold is not yet supported
- It is not yet supported to assign an underflow/overflow to the
input of another counter.
Evaluating every single wire is maybe not the best way to do this, but
it is probably better than writing a very exotic SV construct with
(for-)loops, breaks, and a lot of conditions. Most synthesis tools are
pretty good at recognizing this case-construct and generating a good
mutliplexer.
This required some fundamental changes. One of them is that YAML fields
are now processed in a more systematic way in which all fields are
passed via a dictionary. That way, some of the fields are not bound to
the original object anymore.
This adds initial support for a dynamic bus-protocol to internal
register logic SHIM. The chosen default protocol at this point is AMBA 3
AHB Lite and the logic is still empty.
-> TODO: Adding the widget instantiation showed that it is required
to have a better interface to parametrize ports & signals in the
YAML. At this point, only a limited set of variables are supported.
Furthermore, all remaining Verilator compilation issues in the field are
resolved. Those were mostly related to non-declared wires and wrongly named
wires.
This is caused by register access properties that don't have a
condition. As soon as such a property is encountered, no more branches
shall be added to that register.
This commit only adds package supports for addrmaps. It should be
relatively easy to extend this for regfiles in a future commit.
Furthermore, this commit adds support to _disable_ enums.
Apart from adding regfiles in general (which is mostly a combination of
addrmap and register code), the stride/array_dimension code had to be
revisted to be correct for multi dimensional arrays with multi
dimensional registers.
Lastly, the logger instantiation has been moved to the __init__()
method of `Component`.
These two special kind of resets are now recognized by the compiler and
are propagated to all regfiles, registers, and fields.
Furthermore, every object has a set of resets which will be used to
generate a seperate input section for resets in the addrmap.
Fields that are encoded as enumerations are now recognized by the
application. All relevant information will be saved in the Field Object
and the variables and I/O list will be generated accordingly.
This commit also adds dynamic padding of the I/O and variable lists.
Still lacking is the automatic generation of SV packages.
Now, every snippet of RTL in the YAML file can also hold internal
variables (i.e., signals), input or output ports. Furthermore, the
input/output port lists are replaced by a dictionary to prevent
duplicate entries.
This commit also created a seperate private method for access related
RTL and for the always_ff header.
Furthermore, a bug which caused the singlepulse property to always show
up was resolved.
Lastly, the summary method was made truely public. So, rather than
writing to the RTL list, it now returns a list and the calling
method/function can decide what to do with that list.
All components (e.g., fields, registers, addrmaps) are now children
of a common class Component. This common class has certain common
methods such as get_ports(), get_rtl(), or create_logger().
The AddrMap is now prepared to support alias registers by saving the
registers in a dictionary. That way, registers can easily be accessed
once an alias to a register is found. Furthermore, the addrmap template
is now also loaded from a YAML file. Lastly, the first preparements to
insert ports into the addrmap module are made.
For templates, the indents do not need to be added anymore to the
template. Now, a seperate method will automatically indent the RTL
based on simple rules (e.g., increment indent if `begin` is found).
The CLI also supports settings for the tabs (i.e., real tabs or spaces
and the tab width).
A lot of functionality from the __init__() method of the field class
got reorganized. More logic will be reorganized in the future.
Previously, the SystemVerilog was simply written to the shell. This
started to become too long to be readable. Now, the application dumps
everything to the output directory that is defined on the command line
(or the default).
Temporary workaround: the AddrMap component's RTL is completely
overwritten by the Register's RTL. This is temporary until the AddrMap
also uses a YAML file.
By using a dictionary, it will be easier to mix & match the RTL
order dependend on the properties of the field.
This commit also adds anded/ored/xored properties.
The compiler in this commit is still useless and only contains a
very rough skeleton of the code. SRDL2SV is only able to
create a simple register with hw=rw/sw=rw fields.
Dennis Potter