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Author SHA1 Message Date
Dennis
8df25ece01 Closes #10: sw read/write side-effects now honor byte-enables if enabled 2021-10-31 22:36:51 -07:00
Dennis
22a822c097 Add initial version of sofware access property tests 
At this point, only the read-side-effect tests are implemented.
 2021-10-31 21:56:08 -07:00
Dennis
d4d5868382 Update Makefile to rebuild on srdl2sv changes and better error reporting 2021-10-31 21:54:11 -07:00
Dennis
f0f2ef3d78 Add module description to test_simple_rw_reg.py 2021-10-31 19:43:14 -07:00
Dennis
247f1a7575 Update CLI arguments in README description 2021-10-31 19:35:36 -07:00
Dennis
6c9df1cc02 Add Makefiles in example/ to easily rebuild all examples 2021-10-31 16:38:27 -07:00
Dennis
82b2490256 Update examples with changes from a43cd2e (issue #7) 2021-10-31 16:01:44 -07:00
Dennis
a43cd2ea6c Closes #7: Add flag that disables unpacked arrays 2021-10-31 15:58:31 -07:00
Dennis
a871e9a906 Add example to show handling of SystemRDL enums 2021-10-31 13:59:51 -07:00
Dennis
0371bef439 Long CLI arguments now use dashes rather than underscores 2021-10-31 13:53:11 -07:00
Dennis
ed167c05de Update AMBA 3 AHB Lite widget in examples with 33c92c8 (issue #9) 2021-10-30 23:35:38 -07:00
Dennis
33c92c8994 Closes #9: Error returns from regblock now actually get processed by AHB widget 2021-10-30 23:30:55 -07:00
Dennis
031e413d17 Fix test_simple_rw_reg.test_illegal_address so that it always recognizes issue #9 
Before this fix, the bug would only pop up for addresses that were
dividable by 4. Otherwise, the AMBA AHB 3 Lite widget would return an
error response because of an illegal HSIZE/HADDR combination.
 2021-10-30 23:27:14 -07:00
Dennis
7efe7c4cea Update examples with changes from e46e51f and a148e8b 
The former commit implements fixes that were required for issue #8. The
latter only updated the link to report bugs.
 2021-10-30 19:38:43 -07:00
Dennis
a148e8bbd1 Update link in header to report bugs 2021-10-30 19:37:02 -07:00
Dennis
e46e51f3cf Closes #8: Certain fields shall be implemented as wires or constants 
The software now detects whether a field shall be implemented with
flops, with wires, or as a constant. Everything should now follow Table
12 and Section 9.5.1 of the SystemRDL 2.0 LRM.
 2021-10-30 19:33:14 -07:00
Dennis
5a00d48c34 Add RDL example with compiled hierarchical regfiles 2021-10-28 22:55:28 -07:00
Dennis
738be4ddc4 Update README.md with output-file information 2021-10-27 23:57:15 -07:00
Dennis
e6cfec9c32 Update srdl2sv examples with widget<->interface changes 
These changes were introduced in 85f7808 in order to close #4.
 2021-10-27 23:33:42 -07:00
Dennis
85f7808362 Closes #4: Add support for hierarchical addrmaps 
Every time an addrmap is detected within another addrmap, a new context
will be opened and a separate RTL file will be created.

All addrmaps will have the same bus-wdiget, but it might be possible
that different addrmaps have different maximum regwidths. For that
reason, it was necessary to change the non-generic srd2sv_if_pkg to a
parametrizable interface.

Almost all changes to the templates in this commit are due to name
changes from 'b2r' and 'r2b' to 'widget_if'.
 2021-10-27 23:27:29 -07:00
Dennis
ac693f0c02 Change default logging settings 
STDOUT now will get INFO-level logging by default. The file output will
get no logging by default.
 2021-10-27 23:22:27 -07:00
Dennis
b8e9adb1f0 Add hierarchical interrupts under examples 
The SystemRDL that was added comes from Section 17.2 "Understanding
hierarchical interrupts in SystemRDL" of the SystemRDL 2.0 LRM. The
present code succesfully compiles.
 2021-10-24 23:33:01 -07:00
Dennis
eb3f1dd57e Resolve UnboundLocalError bug when SignalNodes are instantiated 
This happened in AddrMap and RegFile because a the width of a new
variable 'new_child' is performed. However, SignalNodes will not create
such a child.
 2021-10-24 23:19:22 -07:00
Dennis
27c5931101 Add option to add no bus-widget 
If this option is defined, there will be a direct interface to the b2r
and r2b interface. The structs will be flattened out to wires for legacy
reasons.

This closes #3.
 2021-10-24 22:09:16 -07:00
Dennis
0ab368113e Move MIT LICENSE to templates & widgets directory 
That way, Github should be able to auto-detect that srdl2sv itself is
licensed under the GPLv3 license.
 2021-10-24 20:34:06 -07:00
Dennis Potter
d032e77ed8 Fix layout of GPLv3 license 2021-10-24 20:00:23 -07:00
Dennis
b6af2c154c Update Git address to Github in README.md 2021-10-24 15:55:43 -07:00
Dennis
6719d21423 Fix simple_rw_reg.rdl so that the test passes 
The register was defined as a 64-bit register but the test was written
under the assumption it's a 32-bit register. Furthermore, the hardware
write-enable flag had to be set since all values would otherwise be
overwritten immediately.
 2021-10-24 15:43:44 -07:00
Dennis
c4964e0c57 Remove redundant example-file 2021-10-24 14:03:46 -07:00
Dennis
25b562ca65 Update warning and license description in README.md 2021-10-24 13:49:59 -07:00
Dennis
9ac58367ff Add installation instructions to README.md 2021-10-24 13:22:09 -07:00
Dennis
7c55cfaa8e Logger should always lazy evaluate variables 2021-10-24 12:36:17 -07:00
Dennis
49d1b598f0 Add setup.py to repository to install srdl2sv 2021-10-24 12:14:03 -07:00
Dennis
ec02290bbe Move several methods to common Components ancestor 
For example, most methods relating to dimensions or genvars were moved
to the Components class.

Furthermore, some more care was taken of _ or __ prefixes for methods:

    - No method-prefix: Public variable that is will be called by
                        non-related functions and methods.
    - _  method-prefix: Method will be called by class or class that
                        inerhits class
    - __ method-prefix: Method will be called by class itself only
 2021-10-24 00:07:59 -07:00
Dennis
20cec0c2a3 Add missing example RDL file 'simple_rw_reg.rdl' 2021-10-20 23:51:48 -07:00
Dennis
abf3fac24f Minor clean up, mostly Python Lint warnings 2021-10-20 23:51:07 -07:00
Dennis
1ed801a565 Add simple example with 1-D, 2-D, and 3-D registers 2021-10-20 22:34:37 -07:00
Dennis
2da71dabf1 Update README.md to latest feature set 2021-10-20 22:25:07 -07:00
Dennis
1b011ff593 Replace SW Mux Entry by a dataclass, rather than an (unnamed) tuple 2021-10-19 23:58:02 -07:00
Dennis
d80224c43d Do not generate seperate comparisons for cpu interface mux 
Rather, use the activate-signals that get generated anyway.
 2021-10-19 23:33:59 -07:00
Dennis
463bc22e12 Add missing 'endgenerate' in srdl2sv_amba3ahblite.sv 2021-10-19 23:26:14 -07:00
Dennis
5e47ff664a Add option to disable byte-enables 2021-10-18 23:48:14 -07:00
Dennis
4d3f302a54 Add initial support for memory type registers 2021-10-18 23:40:19 -07:00
Dennis
fd7acae701 Update systemrdl-compiler version in requirements.txt 2021-10-18 23:07:15 -07:00
Dennis
9046dcf3e3 Description in regfile.yaml now says 'regfile' and not 'register' 2021-10-18 23:06:21 -07:00
Dennis
e05408e8a1 Add support for inline-comments 
It is possible to enable them for:

- fields
- registers
- regfiles
- addrmaps
 2021-10-17 00:53:22 -07:00
Dennis
16d1774cd2 Remove log.py TODO that got already implemented 2021-10-14 23:29:19 -07:00
Dennis
b23ddded74 Package with enums shall not be dumped if no enums are present 2021-10-14 23:22:01 -07:00
Dennis
6e355c62af Add support for rsvdset and rsvdsetX 2021-10-14 23:16:30 -07:00
Dennis
4ba047dd2a Extend test_simple_rw_reg with 3 more tests 
The following tests are now included:

    - Check access to registers over AHB bus
    - Check access to register over HW interface
    - Check access to register over HW interface if hw_wr-input
      is disabled.
    - Check if the slave responds with a correct error sequence if
      an illegal address is accessed.
 2021-10-11 23:49:31 -07:00