61 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Dennis	8d86010a0a	Tweak default widths of I/O ports	2021-05-15 18:04:43 +02:00
Dennis	7c4f681241	Add SW read- and write wires, including assignment	2021-05-15 18:00:22 +02:00
Dennis	4b9ad7ad1b	Fix SW write wire and improve I/O packed dimension	2021-05-15 18:00:02 +02:00
Dennis	4738cbfe6c	Add support for 1 packed and 26 unpacked dimensions in addrmap's I/O	2021-05-15 01:17:06 +02:00
Dennis	cecb73f07a	Fundamental changes to the architecture of component classes ... All components (e.g., fields, registers, addrmaps) are now children of a common class Component. This common class has certain common methods such as get_ports(), get_rtl(), or create_logger(). The AddrMap is now prepared to support alias registers by saving the registers in a dictionary. That way, registers can easily be accessed once an alias to a register is found. Furthermore, the addrmap template is now also loaded from a YAML file. Lastly, the first preparements to insert ports into the addrmap module are made. For templates, the indents do not need to be added anymore to the template. Now, a seperate method will automatically indent the RTL based on simple rules (e.g., increment indent if `begin` is found). The CLI also supports settings for the tabs (i.e., real tabs or spaces and the tab width). A lot of functionality from the __init__() method of the field class got reorganized. More logic will be reorganized in the future.	2021-05-15 00:29:59 +02:00
Dennis	59b91536ed	Propgate logger through components and let top-level write SV ... Previously, the SystemVerilog was simply written to the shell. This started to become too long to be readable. Now, the application dumps everything to the output directory that is defined on the command line (or the default). Temporary workaround: the AddrMap component's RTL is completely overwritten by the Register's RTL. This is temporary until the AddrMap also uses a YAML file.	2021-05-11 00:28:52 +02:00
Dennis	27c4e9de3c	Add proper logging mechanism to application ... This mechanism has custom coloring, support to dump in file and on the commandline and support to turn either or both off. cli/cli.py provies a function that can be called in each module to instantiate a logger for that module.	2021-05-10 00:59:52 +02:00
Dennis	c32bfdd8c0	Change way SV keyword 'else' is added to access_rtl ... At this point, it is still added in an for-loop. The reason is that this code might get more extensive and become otherwise unreadable.	2021-05-08 11:52:34 +02:00
Dennis	ea998b7db0	Add argparse.ArgumentParser based CliArguments class ... This wrapper lives in a seperate module and class so that possible processing of arguments can be done before the config dictionary gets passed to the compiler.	2021-05-08 11:17:56 +02:00
Dennis	f1d9ba2656	Change way the order of RTL is determined ... By using a dictionary, it will be easier to mix & match the RTL order dependend on the properties of the field. This commit also adds anded/ored/xored properties.	2021-05-04 00:23:14 +02:00
Dennis	861a020aff	Initial commit of SRDL2SV ... The compiler in this commit is still useless and only contains a very rough skeleton of the code. SRDL2SV is only able to create a simple register with hw=rw/sw=rw fields.	2021-05-02 00:58:43 +02:00