126 Commits

Author	SHA1	Message	Date
Dennis	d8add0d5f2	Add more padding between 'input' and name of reset-signal	2021-11-26 16:52:46 -08:00
Dennis	ae83dceb7a	Closes #13: I/O ports are now grouped and are tied to the register the belong to	2021-11-26 16:32:36 -08:00
Dennis	719b013b88	Fix Python lint warnings related to logging	2021-11-07 11:44:07 -08:00
Dennis	33b6e2e946	Fix regression in OnRead and OnWrite properties ... The following tests were failing: - test_swacc_properties.test_rclr_rset - test_swacc_properties.test_rclr_rset_hw_precedence The reason for this failure was incorrect usage of the assignment expression. Due to the lack of parentheses, the onread/onwrite variable would mostly evaluate to False.	2021-11-07 11:36:05 -08:00
Dennis	3e7344a79c	Fix wrong scope names and compilation issues with external aliases	2021-11-07 11:19:03 -08:00
Dennis	0887372dbd	Fix alias bugs introduced when adding external registers ... Furthermore, some compilation bugs were added when optimizing away swacc and swmod wires when not required.	2021-11-06 22:45:34 -07:00
Dennis	17c1b9b9a0	Fix bug with static values for saturate/threshold values	2021-11-06 18:24:42 -07:00
Dennis	b44813e0c5	Fix addrmap & memory/regfile/register/field-naming collision ... For almost all variables, the addrmap is stripped of the name. However, when a memory/regfile/register/field had the same name as the addrmap, a part of that name would also be stripped.	2021-11-06 18:00:17 -07:00
Dennis	8fbf800c4f	Fix bug with dynamic saturate values and fix Lint warnings ... Two categories Lint warnings occured: - Width mismatches, since integers are 32-bit wide according to the SV LRM. - Constant saturate values, because values could get larger than 32-bit and smaller than 0.	2021-11-06 17:36:45 -07:00
Dennis	5d3fd14144	Fix bug that prevented descriptions from being generated inserted	2021-11-06 10:57:46 -07:00
Dennis	85598af11e	Closes #11: Add flag to turn off error-response on illegal addresses	2021-11-06 10:25:32 -07:00
Dennis	85dc71919e	Fix bug introduced in 95b9a5a4 that broke registers with just 1 byte	2021-11-02 23:28:37 -07:00
Dennis	95b9a5a46a	Gather bit-ranges of byte-enable signal in error-wire ... Previously, the error wire would be assigned like this: assign example_reg_err_mux_in = !((widget_if.r_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3])) || (widget_if.w_vld && (widget_if.byte_en[0] || widget_if.byte_en[1] || widget_if.byte_en[2] || widget_if.byte_en[3]))); Now, this same line is simplified to: assign example_reg_err_mux_in = !((widget_if.r_vld && (|widget_if.byte_en[3:0])) || (widget_if.w_vld && (|widget_if.byte_en[3:0])));	2021-11-02 23:17:28 -07:00
Dennis	8df25ece01	Closes #10: sw read/write side-effects now honor byte-enables if enabled	2021-10-31 22:36:51 -07:00
Dennis	a43cd2ea6c	Closes #7: Add flag that disables unpacked arrays	2021-10-31 15:58:31 -07:00
Dennis	0371bef439	Long CLI arguments now use dashes rather than underscores	2021-10-31 13:53:11 -07:00
Dennis	33c92c8994	Closes #9: Error returns from regblock now actually get processed by AHB widget	2021-10-30 23:30:55 -07:00
Dennis	a148e8bbd1	Update link in header to report bugs	2021-10-30 19:37:02 -07:00
Dennis	e46e51f3cf	Closes #8: Certain fields shall be implemented as wires or constants ... The software now detects whether a field shall be implemented with flops, with wires, or as a constant. Everything should now follow Table 12 and Section 9.5.1 of the SystemRDL 2.0 LRM.	2021-10-30 19:33:14 -07:00
Dennis	85f7808362	Closes #4: Add support for hierarchical addrmaps ... Every time an addrmap is detected within another addrmap, a new context will be opened and a separate RTL file will be created. All addrmaps will have the same bus-wdiget, but it might be possible that different addrmaps have different maximum regwidths. For that reason, it was necessary to change the non-generic srd2sv_if_pkg to a parametrizable interface. Almost all changes to the templates in this commit are due to name changes from 'b2r' and 'r2b' to 'widget_if'.	2021-10-27 23:27:29 -07:00
Dennis	ac693f0c02	Change default logging settings ... STDOUT now will get INFO-level logging by default. The file output will get no logging by default.	2021-10-27 23:22:27 -07:00
Dennis	eb3f1dd57e	Resolve UnboundLocalError bug when SignalNodes are instantiated ... This happened in AddrMap and RegFile because a the width of a new variable 'new_child' is performed. However, SignalNodes will not create such a child.	2021-10-24 23:19:22 -07:00
Dennis	27c5931101	Add option to add no bus-widget ... If this option is defined, there will be a direct interface to the b2r and r2b interface. The structs will be flattened out to wires for legacy reasons. This closes #3.	2021-10-24 22:09:16 -07:00
Dennis	0ab368113e	Move MIT LICENSE to templates & widgets directory ... That way, Github should be able to auto-detect that srdl2sv itself is licensed under the GPLv3 license.	2021-10-24 20:34:06 -07:00
Dennis	7c55cfaa8e	Logger should always lazy evaluate variables	2021-10-24 12:36:17 -07:00
Dennis	49d1b598f0	Add setup.py to repository to install srdl2sv	2021-10-24 12:14:03 -07:00
Dennis	ec02290bbe	Move several methods to common Components ancestor ... For example, most methods relating to dimensions or genvars were moved to the Components class. Furthermore, some more care was taken of _ or __ prefixes for methods: - No method-prefix: Public variable that is will be called by non-related functions and methods. - _ method-prefix: Method will be called by class or class that inerhits class - __ method-prefix: Method will be called by class itself only	2021-10-24 00:07:59 -07:00
Dennis	abf3fac24f	Minor clean up, mostly Python Lint warnings	2021-10-20 23:51:07 -07:00
Dennis	2da71dabf1	Update README.md to latest feature set	2021-10-20 22:25:07 -07:00
Dennis	1b011ff593	Replace SW Mux Entry by a dataclass, rather than an (unnamed) tuple	2021-10-19 23:58:02 -07:00
Dennis	d80224c43d	Do not generate seperate comparisons for cpu interface mux ... Rather, use the activate-signals that get generated anyway.	2021-10-19 23:33:59 -07:00
Dennis	463bc22e12	Add missing 'endgenerate' in srdl2sv_amba3ahblite.sv	2021-10-19 23:26:14 -07:00
Dennis	5e47ff664a	Add option to disable byte-enables	2021-10-18 23:48:14 -07:00
Dennis	4d3f302a54	Add initial support for memory type registers	2021-10-18 23:40:19 -07:00
Dennis	9046dcf3e3	Description in regfile.yaml now says 'regfile' and not 'register'	2021-10-18 23:06:21 -07:00
Dennis	e05408e8a1	Add support for inline-comments ... It is possible to enable them for: - fields - registers - regfiles - addrmaps	2021-10-17 00:53:22 -07:00
Dennis	16d1774cd2	Remove log.py TODO that got already implemented	2021-10-14 23:29:19 -07:00
Dennis	b23ddded74	Package with enums shall not be dumped if no enums are present	2021-10-14 23:22:01 -07:00
Dennis	6e355c62af	Add support for rsvdset and rsvdsetX	2021-10-14 23:16:30 -07:00
Dennis	ed08d4bd35	Fix external-register bug where the sw_rd-wire is missing ... This was introduced in dc37c879 because sw_rd-wires got removed here for registers that don't need it.	2021-10-06 23:39:04 -07:00
Dennis	57d8050d56	Fix bug in bus-width of amba3ahblite-widget's instantiation	2021-10-06 23:28:48 -07:00
Dennis	ace4238ccf	Fix bug in external read-interface ... In dc37c879, some properties got saved in self.properties of a Component. In that commit, self.properties['sw_rd'] never got set. For that reason, external registers with a read-interface were broken.	2021-10-06 23:20:55 -07:00
Dennis	aa770073c4	Ensure that file-log gets dumped in --out_dir	2021-10-03 23:31:22 -07:00
Dennis	c4dca87ab5	Ensure that HSIZE is flopped and that data is shifted according to HADDR/HSIZE	2021-10-03 23:22:54 -07:00
Dennis	694f7c124e	Make stickybit available for non-intr fields and add support for sticky	2021-10-03 15:48:27 -07:00
Dennis	f30dce67c2	Give all genvars an gv_ prefix to prevent collisions	2021-10-02 00:38:31 -07:00
Dennis	dc37c87944	Ensure that sw_rd/sw_wr wires are only generated if they are required	2021-10-02 00:32:04 -07:00
Dennis	8756945a6d	Repair multi-enumerations in one regfile bug ... When a regfile did use enumerations from multiple scopes this messed up the eventual packages because every regfile only assumed 1 scope. This is fixed now. TODO: Check what happens if enums are defined in the register scope.	2021-09-30 00:11:50 -07:00
Dennis	d3bfdeb3f0	Buswidth is now variable, based on widest register ... Fixes #2.	2021-09-26 21:16:49 -07:00
Dennis	6359883c27	Finish initial version of interrupt suport, closes #1 ... The software is now able to create most interrupt combinations of Section 9.9 of the SystemRDL 2.0 LRM. It supports stickybit/non-stickybit interrupts, it support posedge, negedge, bothedge, and level interrupts, and it is able to generate all surrounding logic. This commit also fixes a reset-bug that caused registers that were reset to 0 to be not reset (because 'if not reset_value' will return True if the 'reset_value' is 0).	2021-09-26 19:40:04 -07:00