Commit Graph

124 Commits

Author SHA1 Message Date
85f7808362
Closes #4: Add support for hierarchical addrmaps
Every time an addrmap is detected within another addrmap, a new context
will be opened and a separate RTL file will be created.

All addrmaps will have the same bus-wdiget, but it might be possible
that different addrmaps have different maximum regwidths. For that
reason, it was necessary to change the non-generic srd2sv_if_pkg to a
parametrizable interface.

Almost all changes to the templates in this commit are due to name
changes from 'b2r' and 'r2b' to 'widget_if'.
2021-10-27 23:27:29 -07:00
ac693f0c02
Change default logging settings
STDOUT now will get INFO-level logging by default. The file output will
get no logging by default.
2021-10-27 23:22:27 -07:00
b8e9adb1f0
Add hierarchical interrupts under examples
The SystemRDL that was added comes from Section 17.2 "Understanding
hierarchical interrupts in SystemRDL" of the SystemRDL 2.0 LRM. The
present code succesfully compiles.
2021-10-24 23:33:01 -07:00
eb3f1dd57e
Resolve UnboundLocalError bug when SignalNodes are instantiated
This happened in AddrMap and RegFile because a the width of a new
variable 'new_child' is performed. However, SignalNodes will not create
such a child.
2021-10-24 23:19:22 -07:00
27c5931101
Add option to add no bus-widget
If this option is defined, there will be a direct interface to the b2r
and r2b interface. The structs will be flattened out to wires for legacy
reasons.

This closes #3.
2021-10-24 22:09:16 -07:00
0ab368113e
Move MIT LICENSE to templates & widgets directory
That way, Github should be able to auto-detect that srdl2sv itself is
licensed under the GPLv3 license.
2021-10-24 20:34:06 -07:00
d032e77ed8
Fix layout of GPLv3 license 2021-10-24 20:00:23 -07:00
b6af2c154c
Update Git address to Github in README.md 2021-10-24 15:55:43 -07:00
6719d21423
Fix simple_rw_reg.rdl so that the test passes
The register was defined as a 64-bit register but the test was written
under the assumption it's a 32-bit register. Furthermore, the hardware
write-enable flag had to be set since all values would otherwise be
overwritten immediately.
2021-10-24 15:43:44 -07:00
c4964e0c57
Remove redundant example-file 2021-10-24 14:03:46 -07:00
25b562ca65
Update warning and license description in README.md 2021-10-24 13:49:59 -07:00
9ac58367ff
Add installation instructions to README.md 2021-10-24 13:22:09 -07:00
7c55cfaa8e
Logger should always lazy evaluate variables 2021-10-24 12:36:17 -07:00
49d1b598f0
Add setup.py to repository to install srdl2sv 2021-10-24 12:14:03 -07:00
ec02290bbe
Move several methods to common Components ancestor
For example, most methods relating to dimensions or genvars were moved
to the Components class.

Furthermore, some more care was taken of _ or __ prefixes for methods:

    - No method-prefix: Public variable that is will be called by
                        non-related functions and methods.
    - _  method-prefix: Method will be called by class or class that
                        inerhits class
    - __ method-prefix: Method will be called by class itself only
2021-10-24 00:07:59 -07:00
20cec0c2a3
Add missing example RDL file 'simple_rw_reg.rdl' 2021-10-20 23:51:48 -07:00
abf3fac24f
Minor clean up, mostly Python Lint warnings 2021-10-20 23:51:07 -07:00
1ed801a565
Add simple example with 1-D, 2-D, and 3-D registers 2021-10-20 22:34:37 -07:00
2da71dabf1
Update README.md to latest feature set 2021-10-20 22:25:07 -07:00
1b011ff593
Replace SW Mux Entry by a dataclass, rather than an (unnamed) tuple 2021-10-19 23:58:02 -07:00
d80224c43d
Do not generate seperate comparisons for cpu interface mux
Rather, use the activate-signals that get generated anyway.
2021-10-19 23:33:59 -07:00
463bc22e12
Add missing 'endgenerate' in srdl2sv_amba3ahblite.sv 2021-10-19 23:26:14 -07:00
5e47ff664a
Add option to disable byte-enables 2021-10-18 23:48:14 -07:00
4d3f302a54
Add initial support for memory type registers 2021-10-18 23:40:19 -07:00
fd7acae701
Update systemrdl-compiler version in requirements.txt 2021-10-18 23:07:15 -07:00
9046dcf3e3
Description in regfile.yaml now says 'regfile' and not 'register' 2021-10-18 23:06:21 -07:00
e05408e8a1
Add support for inline-comments
It is possible to enable them for:

- fields
- registers
- regfiles
- addrmaps
2021-10-17 00:53:22 -07:00
16d1774cd2
Remove log.py TODO that got already implemented 2021-10-14 23:29:19 -07:00
b23ddded74
Package with enums shall not be dumped if no enums are present 2021-10-14 23:22:01 -07:00
6e355c62af
Add support for rsvdset and rsvdsetX 2021-10-14 23:16:30 -07:00
4ba047dd2a
Extend test_simple_rw_reg with 3 more tests
The following tests are now included:

    - Check access to registers over AHB bus
    - Check access to register over HW interface
    - Check access to register over HW interface if hw_wr-input
      is disabled.
    - Check if the slave responds with a correct error sequence if
      an illegal address is accessed.
2021-10-11 23:49:31 -07:00
ed08d4bd35
Fix external-register bug where the sw_rd-wire is missing
This was introduced in dc37c879 because sw_rd-wires got removed
here for registers that don't need it.
2021-10-06 23:39:04 -07:00
57d8050d56
Fix bug in bus-width of amba3ahblite-widget's instantiation 2021-10-06 23:28:48 -07:00
ace4238ccf
Fix bug in external read-interface
In dc37c879, some properties got saved in self.properties of a
Component. In that commit, self.properties['sw_rd'] never got set.
For that reason, external registers with a read-interface were broken.
2021-10-06 23:20:55 -07:00
aa770073c4
Ensure that file-log gets dumped in --out_dir 2021-10-03 23:31:22 -07:00
7d5ddaf47c
Add first simple test with a simple 2-dimensional array 2021-10-03 23:24:16 -07:00
c4dca87ab5
Ensure that HSIZE is flopped and that data is shifted according to HADDR/HSIZE 2021-10-03 23:22:54 -07:00
aada5c5853
Prepare Makefiles for regression flow with CocoTB tests 2021-10-03 18:07:48 -07:00
694f7c124e
Make stickybit available for non-intr fields and add support for sticky 2021-10-03 15:48:27 -07:00
f30dce67c2
Give all genvars an gv_ prefix to prevent collisions 2021-10-02 00:38:31 -07:00
dc37c87944
Ensure that sw_rd/sw_wr wires are only generated if they are required 2021-10-02 00:32:04 -07:00
8756945a6d
Repair multi-enumerations in one regfile bug
When a regfile did use enumerations from multiple scopes this messed up
the eventual packages because every regfile only assumed 1 scope. This
is fixed now.

TODO: Check what happens if enums are defined in the register scope.
2021-09-30 00:11:50 -07:00
d3bfdeb3f0
Buswidth is now variable, based on widest register
Fixes #2.
2021-09-26 21:16:49 -07:00
6359883c27
Finish initial version of interrupt suport, closes #1
The software is now able to create most interrupt combinations of
Section 9.9 of the SystemRDL 2.0 LRM. It supports
stickybit/non-stickybit interrupts, it support posedge, negedge,
bothedge, and level interrupts, and it is able to generate all
surrounding logic.

This commit also fixes a reset-bug that caused registers that were reset
to 0 to be not reset (because 'if not reset_value' will return True if
the 'reset_value' is 0).
2021-09-26 19:40:04 -07:00
c52e59abd0
Add basic interrupt framework
Up to this point, interrupt outputs are generated and intr, enable,
mask, haltenable, and haltmask are supported. stick, stikcybit and the
different types of interrupts are not yet supported.

This commit also removes the option to turn off santiy checking. This is
a bad idea anyway...
2021-09-25 20:49:39 -07:00
8ea1ad97da
Fix AMBA AHB 3 Lite widget so that first register transactions succeed 2021-09-25 13:01:23 -07:00
28edf17a1c
Pull assignment of multiplexer wires into generate for-loop 2021-09-19 23:24:59 -07:00
887164dd52
Flip r_vld and w_vld in <REG>_sw_wr/<REG>_sw_rd assignment 2021-09-15 23:47:36 -07:00
fea0019aa8
Replace old 'reg_clk' name by more generic 'clk'
The reason is that the template will always assume that the
bus signals and the registers are synchronous. Designers should
implement possible synchronization logic outside of this block.
2021-09-15 23:42:52 -07:00
61cd1fbfe3
Add directory that will contain SystemRDL files for tests 2021-09-13 22:09:04 -07:00