159 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Dennis	5e4a954a0c	Add _very incomplete_ AMBA 3 AHB Lite widget ... This is just a start on the first widget. It is still very limited and not yet functional in any way.	2021-08-22 20:38:56 -07:00
Dennis	145ac70123	Add email address to MIT license	2021-08-15 14:12:21 -07:00
Dennis	78742daba7	Add support for 'next' property to fields	2021-08-15 14:10:22 -07:00
Dennis	a74377bae7	Add underflow property and checker if referenced properties exist	2021-08-15 12:56:41 -07:00
Dennis	1d5bc8b75e	Fix assignment of overflow to increment input of counter	2021-08-15 12:28:07 -07:00
Dennis	fd75e4c84c	Update systemrdl-compiler to v1.19.0 ... The main difference in this release (https://github.com/SystemRDL/systemrdl-compiler/releases/tag/v1.19.0) is that FieldNode.get_property('resetsignal') will now default to finding the nearest in-scope field reset signal if not explicitly set. The same is true for the cpuif-signal. Before this commit, the addmap-class searched for resetsignal and cpuif signals and saved it for the fields to be picked up later. This code is now not required anymore	2021-08-15 11:46:40 -07:00
Dennis	1d50b2b457	Add incrthreshold/decrthreshold support ... It is still not possible to assign overflow/threshold signals to any input of a different register!	2021-06-29 00:14:51 +02:00
Dennis	18204d9a3e	Improve counter property ... The counter now covers more corner cases regarding saturation. Furthermore, a bug that caused incr & decr-counters to always inadvertently increment and decrement, even if only one of the two signals was set. Furthermore, the overflow signal is now generated in RTL. Still missing: - incrthreshold/decrthreshold is not yet supported - It is not yet supported to assign an underflow/overflow to the input of another counter.	2021-06-28 23:58:45 +02:00
Dennis	4144329f3f	Add comment to delineate between counters and multiplexer assignment	2021-06-28 23:57:32 +02:00
Dennis	a0dd59d19a	Add hwenable and hwmask property	2021-06-28 12:48:17 +02:00
Dennis	c00550a166	Add hwset & hwclr properties	2021-06-28 00:37:54 +02:00
Dennis	9385f59ac7	Add counters (w/o threshold property and w/o an overflow property) ... Saturating and non-saturating counters are supported. Furthermore, dynamic and static incrvalues and the incrwidth property is supported.	2021-06-27 17:04:48 +02:00
Dennis	f50d65d2d2	Fix path in logger object ... For addrmaps, the addrmaps appeared twice. It was better anyway to use a variable name that gets build in create_underscored_path(). This method was not yet present when the logger was first instantiated.	2021-06-27 11:09:10 +02:00
Dennis	5ed7cccd7f	Cleanup __add_swmod_swacc and extend verbosity of warnings/debug	2021-06-27 00:21:41 +02:00
Dennis	2e22d82146	Add swmod and swacc properties and fix field-range bug	2021-06-27 00:09:28 +02:00
Dennis	95fef548cf	Add header with license and generation information to addrmap	2021-06-26 11:37:56 +02:00
Dennis	6deb772196	Add LICENSEs to srdl2sv ... The software itself is licensed under the copy-left GPL-3.0 license. All RTL (i.e., templates and widgets) are licensed under the MIT license. Therefore, the generated RTL will not be subject to the GPL-3.0 but to the MIT license.	2021-06-26 11:08:13 +02:00
Dennis	baf08d2343	Add bus_clk/bus_rst_n ports to widget (rather than (only) reg_clk)	2021-06-25 11:50:06 +02:00
Dennis	6565c33445	Resolve Python Lint warnings (e.g., unnecessary list comprehensions)	2021-06-25 11:46:18 +02:00
Dennis	c7f571b909	Fix missing multiplexer entries for single-dimension registers	2021-06-25 11:45:47 +02:00
Dennis	695de2d330	Add <<INDENT>> and <<UNINDENT>> helpers to template ... This allows a designer to add markers to the template to indicate where a new level of indentation should start or end. This is apart fromt he auto-indents caused by "case", "begin", or "{".	2021-06-25 11:33:57 +02:00
Dennis	01a696c2b3	Add default value to mux to prevent an inferred latch	2021-06-25 01:35:55 +02:00
Dennis	ce4782c11d	Pull declaration of variables outside of generate scope ... This ensures that code is compilation clean again. Prior to this change, the multiplexer was reading from variables that were declared inside of generate-scopes. Furthermore, a small bug regarding the dimension detection of registers was fixed. If a register wasn't multidimensional itself, but its parent is, the multidimensionalness wasn't detected.	2021-06-25 01:20:32 +02:00
Dennis	3089edc20d	Add indentation to case-block	2021-06-24 01:05:55 +02:00
Dennis	31179eeecc	Add get_package_rtl()-method to regfiles	2021-06-24 01:00:36 +02:00
Dennis	0db14e8815	Add missing sw_rd_bus-input port to widget	2021-06-24 00:58:42 +02:00
Dennis	32c6fc3c4a	Add read-multiplexer logic ... Evaluating every single wire is maybe not the best way to do this, but it is probably better than writing a very exotic SV construct with (for-)loops, breaks, and a lot of conditions. Most synthesis tools are pretty good at recognizing this case-construct and generating a good mutliplexer.	2021-06-23 01:03:11 +02:00
Dennis	b2c756af41	Add support for alias registers ... This required some fundamental changes. One of them is that YAML fields are now processed in a more systematic way in which all fields are passed via a dictionary. That way, some of the fields are not bound to the original object anymore.	2021-06-12 01:28:29 +02:00
Dennis	9deb28ce4e	Add initial version of widget-code and fix remaining SV compiler errors ... This adds initial support for a dynamic bus-protocol to internal register logic SHIM. The chosen default protocol at this point is AMBA 3 AHB Lite and the logic is still empty. -> TODO: Adding the widget instantiation showed that it is required to have a better interface to parametrize ports & signals in the YAML. At this point, only a limited set of variables are supported. Furthermore, all remaining Verilator compilation issues in the field are resolved. Those were mostly related to non-declared wires and wrongly named wires.	2021-06-05 15:37:09 +02:00
Dennis	21abdefac0	Add genvar declaration to addrmap	2021-06-03 18:07:17 +02:00
Dennis	f4432f5b49	Add check for uniqueness of enum member names within a scope	2021-06-03 16:46:49 +02:00
Dennis	ec492d619a	Fix widths in OnWrite and OnRead properties	2021-06-03 16:11:58 +02:00
Dennis	ee20126da6	Add missing 'endmodule' keyword to addrmap	2021-06-03 12:56:26 +02:00
Dennis	22f88efcd8	Fix compile error because of multiple else branches ... This is caused by register access properties that don't have a condition. As soon as such a property is encountered, no more branches shall be added to that register.	2021-06-03 12:53:39 +02:00
Dennis	5d76830931	Fix generate/endgenerate and end of generate loops in regfiles ... Previously, the beginning of a new loop always caused a new generate keyword, which is wrong.	2021-06-03 12:15:27 +02:00
Dennis	4f6010eed2	Dump addrmap packages with enums ... This commit only adds package supports for addrmaps. It should be relatively easy to extend this for regfiles in a future commit. Furthermore, this commit adds support to _disable_ enums.	2021-06-03 12:02:27 +02:00
Dennis	fa7adf0a54	Add initial README and logo	2021-05-31 23:23:56 +02:00
Dennis	077dcde0cf	Add requirements.txt	2021-05-31 00:39:19 +02:00
Dennis	8a82d37737	Add regfile capabilities ... Apart from adding regfiles in general (which is mostly a combination of addrmap and register code), the stride/array_dimension code had to be revisted to be correct for multi dimensional arrays with multi dimensional registers. Lastly, the logger instantiation has been moved to the __init__() method of `Component`.	2021-05-31 00:37:41 +02:00
Dennis	2a3cc9505e	Add support for field_reset and cpuif_reset ... These two special kind of resets are now recognized by the compiler and are propagated to all regfiles, registers, and fields. Furthermore, every object has a set of resets which will be used to generate a seperate input section for resets in the addrmap.	2021-05-24 14:42:24 +02:00
Dennis	44c87af8cb	Fix active_low/active_high reset bug ... A negation was added for active_high, rather than an active_low reset.	2021-05-24 11:49:51 +02:00
Dennis	b7c1a12179	Add support for enumeration encoding ... Fields that are encoded as enumerations are now recognized by the application. All relevant information will be saved in the Field Object and the variables and I/O list will be generated accordingly. This commit also adds dynamic padding of the I/O and variable lists. Still lacking is the automatic generation of SV packages.	2021-05-24 11:41:45 +02:00
Dennis	085e2ea2dc	Provide more advanced way of adding internal signals or ports ... Now, every snippet of RTL in the YAML file can also hold internal variables (i.e., signals), input or output ports. Furthermore, the input/output port lists are replaced by a dictionary to prevent duplicate entries.	2021-05-23 17:46:48 +02:00
Dennis	c5755bf104	Removed genvars in case only 1 dimension with 1 entry is used	2021-05-17 00:15:43 +02:00
Dennis	203f1e1b36	Add swwe and swwel properties ... Note: swwe=True & swwel=True are not yet supported (since they don't really make sense). At this point, references are (partly) supported.	2021-05-16 23:53:58 +02:00
Dennis	92d61dd7c8	Add onread/onwrite properties to field class ... This commit also created a seperate private method for access related RTL and for the always_ff header. Furthermore, a bug which caused the singlepulse property to always show up was resolved. Lastly, the summary method was made truely public. So, rather than writing to the RTL list, it now returns a list and the calling method/function can decide what to do with that list.	2021-05-16 12:49:17 +02:00
Dennis	3acd7516d3	Fix bug in <REG>_sw_wr/<REG>_sw_rd for non-array registers ... In case a register isn't instantiated as an array, the stride value the compiler returns is set to 'None'. The RTL generator should translate it to '0' (since it doesn't matter anyway).	2021-05-16 12:24:52 +02:00
Dennis	a59668de87	Ensure that component logs don't propagate to the root	2021-05-16 12:17:52 +02:00
Dennis	8d86010a0a	Tweak default widths of I/O ports	2021-05-15 18:04:43 +02:00
Dennis	7c4f681241	Add SW read- and write wires, including assignment	2021-05-15 18:00:22 +02:00