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Author	SHA1	Message	Date
Dennis	44c87af8cb	Fix active_low/active_high reset bug ... A negation was added for active_high, rather than an active_low reset.	2021-05-24 11:49:51 +02:00
Dennis	b7c1a12179	Add support for enumeration encoding ... Fields that are encoded as enumerations are now recognized by the application. All relevant information will be saved in the Field Object and the variables and I/O list will be generated accordingly. This commit also adds dynamic padding of the I/O and variable lists. Still lacking is the automatic generation of SV packages.	2021-05-24 11:41:45 +02:00
Dennis	085e2ea2dc	Provide more advanced way of adding internal signals or ports ... Now, every snippet of RTL in the YAML file can also hold internal variables (i.e., signals), input or output ports. Furthermore, the input/output port lists are replaced by a dictionary to prevent duplicate entries.	2021-05-23 17:46:48 +02:00
Dennis	c5755bf104	Removed genvars in case only 1 dimension with 1 entry is used	2021-05-17 00:15:43 +02:00
Dennis	203f1e1b36	Add swwe and swwel properties ... Note: swwe=True & swwel=True are not yet supported (since they don't really make sense). At this point, references are (partly) supported.	2021-05-16 23:53:58 +02:00
Dennis	92d61dd7c8	Add onread/onwrite properties to field class ... This commit also created a seperate private method for access related RTL and for the always_ff header. Furthermore, a bug which caused the singlepulse property to always show up was resolved. Lastly, the summary method was made truely public. So, rather than writing to the RTL list, it now returns a list and the calling method/function can decide what to do with that list.	2021-05-16 12:49:17 +02:00
Dennis	3acd7516d3	Fix bug in <REG>_sw_wr/<REG>_sw_rd for non-array registers ... In case a register isn't instantiated as an array, the stride value the compiler returns is set to 'None'. The RTL generator should translate it to '0' (since it doesn't matter anyway).	2021-05-16 12:24:52 +02:00
Dennis	a59668de87	Ensure that component logs don't propagate to the root	2021-05-16 12:17:52 +02:00
Dennis	8d86010a0a	Tweak default widths of I/O ports	2021-05-15 18:04:43 +02:00
Dennis	7c4f681241	Add SW read- and write wires, including assignment	2021-05-15 18:00:22 +02:00
Dennis	4b9ad7ad1b	Fix SW write wire and improve I/O packed dimension	2021-05-15 18:00:02 +02:00
Dennis	4738cbfe6c	Add support for 1 packed and 26 unpacked dimensions in addrmap's I/O	2021-05-15 01:17:06 +02:00
Dennis	cecb73f07a	Fundamental changes to the architecture of component classes ... All components (e.g., fields, registers, addrmaps) are now children of a common class Component. This common class has certain common methods such as get_ports(), get_rtl(), or create_logger(). The AddrMap is now prepared to support alias registers by saving the registers in a dictionary. That way, registers can easily be accessed once an alias to a register is found. Furthermore, the addrmap template is now also loaded from a YAML file. Lastly, the first preparements to insert ports into the addrmap module are made. For templates, the indents do not need to be added anymore to the template. Now, a seperate method will automatically indent the RTL based on simple rules (e.g., increment indent if `begin` is found). The CLI also supports settings for the tabs (i.e., real tabs or spaces and the tab width). A lot of functionality from the __init__() method of the field class got reorganized. More logic will be reorganized in the future.	2021-05-15 00:29:59 +02:00
Dennis	59b91536ed	Propgate logger through components and let top-level write SV ... Previously, the SystemVerilog was simply written to the shell. This started to become too long to be readable. Now, the application dumps everything to the output directory that is defined on the command line (or the default). Temporary workaround: the AddrMap component's RTL is completely overwritten by the Register's RTL. This is temporary until the AddrMap also uses a YAML file.	2021-05-11 00:28:52 +02:00
Dennis	27c4e9de3c	Add proper logging mechanism to application ... This mechanism has custom coloring, support to dump in file and on the commandline and support to turn either or both off. cli/cli.py provies a function that can be called in each module to instantiate a logger for that module.	2021-05-10 00:59:52 +02:00
Dennis	c32bfdd8c0	Change way SV keyword 'else' is added to access_rtl ... At this point, it is still added in an for-loop. The reason is that this code might get more extensive and become otherwise unreadable.	2021-05-08 11:52:34 +02:00
Dennis	ea998b7db0	Add argparse.ArgumentParser based CliArguments class ... This wrapper lives in a seperate module and class so that possible processing of arguments can be done before the config dictionary gets passed to the compiler.	2021-05-08 11:17:56 +02:00
Dennis	f1d9ba2656	Change way the order of RTL is determined ... By using a dictionary, it will be easier to mix & match the RTL order dependend on the properties of the field. This commit also adds anded/ored/xored properties.	2021-05-04 00:23:14 +02:00
Dennis	861a020aff	Initial commit of SRDL2SV ... The compiler in this commit is still useless and only contains a very rough skeleton of the code. SRDL2SV is only able to create a simple register with hw=rw/sw=rw fields.	2021-05-02 00:58:43 +02:00